公开(公告)号：US20220406778A1

公开(公告)日：2022-12-22

申请号：US17353263

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Biswajeet GUHA ,  Mohit K. HARAN ,  Mohammad HASAN ,  Reken PATEL ,  Sean PURSEL ,  Jake JAFFE

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: Integrated circuit structures having plugged metal gates, and methods of fabricating integrated circuit structures having plugged metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on the STI structure. The gate dielectric material layer and the conductive gate layer are along a side of the dielectric gate plug, and the gate dielectric material layer is in direct contact with an entirety of the side of the dielectric gate plug.

公开(公告)号：US20210090990A1

公开(公告)日：2021-03-25

申请号：US16579077

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Florian GSTREIN ,  Leonard P. GULER ,  Charles H. WALLACE ,  Paul A. NYHUS ,  Curtis WARD ,  Mohit K. HARAN ,  Reken PATEL

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/66

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

公开(公告)号：US20230095402A1

公开(公告)日：2023-03-30

申请号：US17485190

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Elijah V. KARPOV ,  Mohit K. HARAN ,  Reken PATEL ,  Charles H. WALLACE ,  Gurpreet SINGH ,  Florian GSTREIN ,  Eungnak HAN ,  Urusa ALAAN ,  Leonard P. GULER ,  Paul A. NYHUS

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

公开(公告)号：US20210090997A1

公开(公告)日：2021-03-25

申请号：US16579088

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Mohit K. HARAN ,  Reken PATEL ,  Richard E. SCHENKER ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.

公开(公告)号：US20230326794A1

公开(公告)日：2023-10-12

申请号：US18207047

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael HARPER ,  Suzanne S. RICH ,  Charles H. WALLACE ,  Curtis WARD ,  Richard E. SCHENKER ,  Paul NYHUS ,  Mohit K. HARAN ,  Reken PATEL ,  Swaminathan SIVAKUMAR

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/823412 ,  H01L21/823475

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

公开(公告)号：US20200185271A1

公开(公告)日：2020-06-11

申请号：US16637930

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Reken PATEL ,  Hyunsoo PARK ,  Mohit K. HARAN ,  Debashish BASU ,  Curtis W. WARD ,  Ruth A. Brain

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

公开(公告)号：US20250046713A1

公开(公告)日：2025-02-06

申请号：US18921394

申请日：2024-10-21

Applicant: Intel Corporation

Inventor： Mohit K. HARAN ,  Reken PATEL ,  Richard E. SCHENKER ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Self-aligned patterning with colored blocking and resulting structures are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate, and a hardmask layer on the ILD layer. A plurality of conductive interconnect lines is in and spaced apart by the ILD layer and the hardmask layer. The plurality of conductive interconnect lines includes a first interconnect line having a first width. A second interconnect line is immediately adjacent the first interconnect line by a first distance, the second interconnect line having the first width. A third interconnect line is immediately adjacent the second interconnect line by the first distance, the third interconnect line having the first width. A fourth interconnect line is immediately adjacent the third interconnect line by a second distance greater than the first distance, the fourth interconnect line having a second width greater than the first width.

公开(公告)号：US20250006733A1

公开(公告)日：2025-01-02

申请号：US18214898

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Swapnadip GHOSH ,  Chiao-Ti HUANG ,  Amritesh RAI ,  Akitomo MATSUBAYASHI ,  Fariha KHAN ,  Anupama BOWONDER ,  Reken PATEL ,  Chi-Hing CHOI

IPC: H01L27/092 ,  H01L21/8238

Abstract: Integrated circuit structures having differential epitaxial source or drain dent are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. A second sub-fin structure is beneath a second stack of nanowires or fin. A first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.

公开(公告)号：US20240178226A1

公开(公告)日：2024-05-30

申请号：US18437961

申请日：2024-02-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  Michael K. HARPER ,  William HSU ,  Biswajeet GUHA ,  Tahir GHANI ,  Niels ZUSSBLATT ,  Jeffrey Miles TAN ,  Benjamin KRIEGEL ,  Mohit K. HARAN ,  Reken PATEL ,  Oleg GOLONZKA ,  Mohammad HASAN

IPC: H01L27/088 ,  G11C5/06 ,  H01L27/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  G11C5/06 ,  H01L27/0688 ,  H01L29/0669 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.

公开(公告)号：US20230101212A1

公开(公告)日：2023-03-30

申请号：US17958295

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Elijah V. KARPOV ,  Mohit K. HARAN ,  Reken PATEL ,  Charles H. WALLACE ,  Gurpreet SINGH ,  Florian GSTREIN ,  Eungnak HAN ,  Urusa ALAAN ,  Leonard P. GULER ,  Paul A. NYHUS

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/535 ,  H01L29/78

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.