Invention Application
- Patent Title: STACKED DIE CAVITY PACKAGE
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Application No.: US16463638Application Date: 2016-12-27
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Publication No.: US20200185289A1Publication Date: 2020-06-11
- Inventor: Mitul MODI , Robert L. SANKMAN , Debendra MALLIK , Ravindranath V. MAHAJAN , Amruthavalli P. ALUR , Yikang DENG , Eric J. LI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US16/68722 WO 20161227
- Main IPC: H01L23/13
- IPC: H01L23/13 ; H01L23/498 ; H01L23/31 ; H01L25/065 ; H01L25/18 ; H01L25/00 ; H01L21/56 ; H01L21/48

Abstract:
An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US11328968B2 Stacked die cavity package Public/Granted day:2022-05-10
Information query
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