公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

申请人： Intel Corporation

发明人： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

摘要： Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20220117089A1

公开(公告)日：2022-04-14

申请号：US17560004

申请日：2021-12-22

申请人： Intel Corporation

发明人： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

IPC分类号： H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00

摘要： Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20190393143A1

公开(公告)日：2019-12-26

申请号：US16017671

申请日：2018-06-25

申请人： Intel Corporation

发明人： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC分类号： H01L23/498 ,  H01L21/48

摘要： Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20190311916A1

公开(公告)日：2019-10-10

申请号：US16317789

申请日：2016-07-14

申请人： Intel Corporation

发明人： Sri Chaitra CHAVALI ,  Siddharth K. ALUR ,  Amanda E. SCHUCKMAN ,  Amruthavalli Palla ALUR ,  Islam A. SALAMA ,  Yikang DENG ,  Kristof DARMAWIKARTA

IPC分类号： H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

摘要： Various embodiments of the disclosure are directed to a semiconductor package and a method for fabrication of the semiconductor package. Further, disclosed herein are systems and methods that are directed to using a photoimageable dielectric (PID) layer with substantially similar mechanical properties as that of a mold material. The disclosure can be used, for example, in the context of bumpless laserless embedded substrate structures (BLESS) technology for wafer/panel level redistribution layer (RDL) and/or fan-out packaging applications. The disclosed embodiments may reduce the need for multiple dry resist film (DFR) lamination steps during various processing steps for semiconductor packaging and can also facilitate multiple layer counts due to the availability of thin PID materials.

公开(公告)号：US20190287934A1

公开(公告)日：2019-09-19

申请号：US15921511

申请日：2018-03-14

申请人： Intel Corporation

发明人： Yikang DENG ,  Jonathan ROSCH ,  Andrew BROWN ,  Junnan ZHAO

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01F27/40

摘要： Techniques for fabricating a cored or coreless semiconductor package having one or more magnetic bilayer structures embedded therein are described. A magnetic bilayer structure includes a magnetic layer and a dielectric layer. For one technique, fabricating a cored or coreless semiconductor package includes: depositing a seed layer on a build-up layer; forming a raised pad structure and a trace on the seed layer; removing one or more uncovered portions of the seed layer to uncover top surfaces of one or more portions of the build-up layer; applying a magnetic bilayer structure on the raised pad structure, the trace, any unremoved portion of the seed layer, and the top surfaces of the one or more portions of the build-up layer, the magnetic bilayer structure comprises a magnetic layer and a dielectric layer; and forming a conductive structure on the raised pad structure. Other techniques are also described.

公开(公告)号：US20220238402A1

公开(公告)日：2022-07-28

申请号：US17720202

申请日：2022-04-13

申请人： Intel Corporation

发明人： Mitul MODI ,  Robert L. SANKMAN ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Amruthavalli P. ALUR ,  Yikang DENG ,  Eric J. LI

IPC分类号： H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190274217A1

公开(公告)日：2019-09-05

申请号：US15910288

申请日：2018-03-02

申请人： Intel Corporation

发明人： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

IPC分类号： H05K1/16 ,  H01F27/28 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04

摘要： Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20190272936A1

公开(公告)日：2019-09-05

申请号：US15911549

申请日：2018-03-05

申请人： Intel Corporation

发明人： Chong ZHANG ,  Cheng XU ,  Ying WANG ,  Junnan ZHAO ,  Meizi JIAO ,  Yikang DENG

IPC分类号： H01F27/24 ,  G05F1/10 ,  H01L49/02 ,  H01F41/02

摘要： Embodiments include inductors with embedded magnetic cores and methods of forming such inductors. Some embodiments may include an integrated circuit package that utilizes such inductors. For example, the integrated circuit package may include an integrated circuit die and a multi-phase voltage regulator electrically coupled to the integrated circuit die. In an embodiment, the multi-phase voltage regulator includes a substrate core and a plurality of inductors in the substrate core. In an embodiment, the inductors may include a conductive loop in and around the substrate core. In an embodiment, the conductive loops are electrically coupled to a voltage out line. Embodiments may also include a magnetic core surrounded by the conductive loops. The magnetic core is separated from surfaces of the conductive loops by the substrate core

公开(公告)号：US20200185289A1

公开(公告)日：2020-06-11

申请号：US16463638

申请日：2016-12-27

申请人： Intel Corporation

发明人： Mitul MODI ,  Robert L. SANKMAN ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Amruthavalli P. ALUR ,  Yikang DENG ,  Eric J. LI

IPC分类号： H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

摘要： An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190317285A1

公开(公告)日：2019-10-17

申请号：US16473216

申请日：2017-09-12

申请人： Intel Corporation

发明人： Shawna M. LIFF ,  Henning BRAUNISCH ,  Timothy A. GOSSELIN ,  Prasanna RAGHAVAN ,  Yikang DENG ,  Zhiguo QIAN

IPC分类号： G02B6/42 ,  F21V8/00 ,  G02B6/293

摘要： An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.