An integrated circuit includes a power-on reset (POR) circuit and a digital logic circuit. The POR has first and second control outputs. The POR circuit is configured to generate a first control signal on the first control output responsive to a supply voltage on the supply voltage node exceeding a first threshold voltage and is configured to generate a second control signal on the second control output responsive to the supply voltage exceeding a second threshold voltage. The digital logic circuit has a first control input coupled to the first control output of the POR circuit and has a second control input coupled to the second control output of the POR circuit. The digital logic circuit is configured to initiate a first read transaction responsive to assertion of the first control signal and to initiate a second read transaction responsive to assertion of the second control signal.