- 专利标题: VIA CONTACT PATTERNING METHOD TO INCREASE EDGE PLACEMENT ERROR MARGIN
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申请号: US16574308申请日: 2019-09-18
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公开(公告)号: US20210082805A1公开(公告)日: 2021-03-18
- 发明人: Mohit K. Haran , Daniel James Bahr , Deepak S. Rao , Marvin Young Paik , Seungdo An , Debashish Basu , Kilhyun Bang , Jason W. Klaus , Reken Patel , Charles Henry Wallace , James Jeong , Ruth Amy Brain
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L23/522
- IPC分类号: H01L23/522 ; H01L23/532 ; H01L23/528 ; H01L21/768
摘要:
An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.
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