公开(公告)号：US11764219B2

公开(公告)日：2023-09-19

申请号：US16700064

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Harshitha Vishwanath ,  Renukprasad Hiremath ,  Sukru Yemenicioglu ,  Ranjith Kumar ,  Ruth Amy Brain

IPC: H01L27/092 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/0924 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate, and a cell on the substrate. In an embodiment, the cell comprises a plurality of transistors over the substrate, and a first metal layer over the plurality of transistors. In an embodiment, the first metal layer comprises a first power line, wherein a width of the first power line is entirely within the cell, a second power line, wherein a width of the second power line is entirely within the cell, and a plurality of signal lines between the first power line and the second power line.

公开(公告)号：US11211324B2

公开(公告)日：2021-12-28

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US11652045B2

公开(公告)日：2023-05-16

申请号：US17511656

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/5329

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.

公开(公告)号：US20210183761A1

公开(公告)日：2021-06-17

申请号：US16713867

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Reken Patel ,  Mohit K. Haran ,  Jeremy J. Guttman ,  Shyam B. Kadali ,  Ruth Amy Brain ,  Seyedhamed M Barghi ,  Zhenjun Zhang ,  James Jeong ,  Robert M. Bigwood ,  Charles Henry Wallace

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311

Abstract: Disclosed herein are line patterning techniques for integrated circuit (IC) devices, as well as related devices and assemblies In some embodiments, a patterned line region of an IC device may include: a first conductive line; a second conductive line parallel to the first conductive line; a conductive bridge between the first conductive line and the second conductive line, wherein the conductive bridge is coplanar with the first conductive line and the second conductive line; and pitch-division artifacts.

公开(公告)号：US20210082805A1

公开(公告)日：2021-03-18

申请号：US16574308

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Mohit K. Haran ,  Daniel James Bahr ,  Deepak S. Rao ,  Marvin Young Paik ,  Seungdo An ,  Debashish Basu ,  Kilhyun Bang ,  Jason W. Klaus ,  Reken Patel ,  Charles Henry Wallace ,  James Jeong ,  Ruth Amy Brain

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: An example via contact patterning method includes providing a pattern of alternating trench contacts and gates over a support structure. For each pair of adjacent trench contacts and gates, a trench contact is electrically insulated from an adjacent gate by a dielectric material and/or multiple layers of different dielectric materials, and the gates are recessed with respect to the trench contacts. The method further includes wrapping a protective layer of one or more dielectric materials, and a sacrificial helmet material on top of the trench contacts to protect them during the via contact patterning and etch processes for forming via contacts over one or more gates. Such a method may advantageously allow increasing the edge placement error margin for forming via contacts of metallization stacks.