Invention Application
- Patent Title: TRANSISTOR WITH ISOLATION BELOW SOURCE AND DRAIN
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Application No.: US17493695Application Date: 2021-10-04
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Publication No.: US20220028972A1Publication Date: 2022-01-27
- Inventor: Willy RACHMADY , Cheng-Ying HUANG , Matthew V. METZ , Nicholas G. MINUTILLO , Sean T. MA , Anand S. MURTHY , Jack T. KAVALIEROS , Tahir GHANI , Gilbert DEWEY
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/08 ; H01L29/10 ; H01L29/205 ; H01L29/423 ; H01L29/66 ; H01L29/78

Abstract:
A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
Public/Granted literature
- US11923410B2 Transistor with isolation below source and drain Public/Granted day:2024-03-05
Information query
IPC分类: