- 专利标题: Device, a Method Used in Forming a Circuit Structure, a Method Used in Forming an Array of Elevationally-Extending Transistors and a Circuit Structure Adjacent Thereto
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申请号: US17504313申请日: 2021-10-18
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公开(公告)号: US20220037360A1公开(公告)日: 2022-02-03
- 发明人: Paolo Tessariol , Justin B. Dorhout , Indra V. Chary , Jun Fang , Matthew Park , Zhiqiang Xie , Scott D. Stull , Daniel Osterberg , Jason Reece , Jian Li
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 主分类号: H01L27/11582
- IPC分类号: H01L27/11582 ; H01L21/768 ; H01L21/311 ; H01L23/528 ; H01L27/11556 ; H01L21/02 ; H01L29/10 ; H01L23/522 ; H01L27/11575
摘要:
A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
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