-
公开(公告)号:US10446507B2
公开(公告)日:2019-10-15
申请号:US15691303
申请日:2017-08-30
Applicant: Micron Technology, Inc.
Inventor: Hongbin Zhu , Qinglin Zeng , Daniel Osterberg , Merri L. Carlson , Gordon A. Haller , Jeremy Adams
IPC: H01L23/58 , H01L23/528 , H01L23/522 , H01L23/00
Abstract: A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path from proximate a surface of the substrate to an exposed surface of the semiconductor die. A second die ring comprises an electrically conductive material and is disposed around the first die ring. A first electrically conductive interconnect electrically connects the first die ring and to second die ring. Related semiconductor devices and semiconductor dice are disclosed.
-
公开(公告)号:US11177271B2
公开(公告)日:2021-11-16
申请号:US15705179
申请日:2017-09-14
Applicant: Micron Technology, Inc.
Inventor: Paolo Tessariol , Justin B. Dorhout , Indra V. Chary , Jun Fang , Matthew Park , Zhiqiang Xie , Scott D. Stull , Daniel Osterberg , Jason Reece , Jian Li
IPC: H01L27/11582 , H01L21/768 , H01L21/311 , H01L23/528 , H01L27/11556 , H01L21/02 , H01L29/10 , H01L23/522 , H01L27/11575 , H01L27/11565
Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
-
公开(公告)号:US20220037360A1
公开(公告)日:2022-02-03
申请号:US17504313
申请日:2021-10-18
Applicant: Micron Technology, Inc.
Inventor: Paolo Tessariol , Justin B. Dorhout , Indra V. Chary , Jun Fang , Matthew Park , Zhiqiang Xie , Scott D. Stull , Daniel Osterberg , Jason Reece , Jian Li
IPC: H01L27/11582 , H01L21/768 , H01L21/311 , H01L23/528 , H01L27/11556 , H01L21/02 , H01L29/10 , H01L23/522 , H01L27/11575
Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
-
公开(公告)号:US11889695B2
公开(公告)日:2024-01-30
申请号:US17504313
申请日:2021-10-18
Applicant: Micron Technology, Inc.
Inventor: Paolo Tessariol , Justin B. Dorhout , Indra V. Chary , Jun Fang , Matthew Park , Zhiqiang Xie , Scott D. Stull , Daniel Osterberg , Jason Reece , Jian Li
IPC: H01L27/11582 , H10B43/27 , H01L21/768 , H01L21/311 , H01L23/528 , H01L21/02 , H01L29/10 , H01L23/522 , H10B41/27 , H10B43/50 , H10B41/35 , H10B43/10
CPC classification number: H10B43/27 , H01L21/02636 , H01L21/31111 , H01L21/76802 , H01L21/76877 , H01L21/76895 , H01L23/528 , H01L23/5226 , H01L29/1037 , H10B41/27 , H10B41/35 , H10B43/50 , H10B43/10
Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
-
公开(公告)号:US20190081061A1
公开(公告)日:2019-03-14
申请号:US15705179
申请日:2017-09-14
Applicant: Micron Technology, Inc.
Inventor: Paolo Tessariol , Justin B. Dorhout , Indra V. Chary , Jun Fang , Matthew Park , Zhiqiang Xie , Scott D. Stull , Daniel Osterberg , Jason Reece , Jian Li
IPC: H01L27/11582 , H01L21/768 , H01L21/311 , H01L27/11556 , H01L21/02 , H01L29/10 , H01L23/522 , H01L23/528
Abstract: A device comprises an array of elevationally-extending transistors and a circuit structure adjacent and electrically coupled to the elevationally-extending transistors of the array. The circuit structure comprises a stair step structure comprising vertically-alternating tiers comprising conductive steps that are at least partially elevationally separated from one another by insulative material. Operative conductive vias individually extend elevationally through one of the conductive steps at least to a bottom of the vertically-alternating tiers and individually electrically couple to an electronic component below the vertically-alternating tiers. Dummy structures individually extend elevationally through one of the conductive steps at least to the bottom of the vertically-alternating tiers. Methods are also disclosed.
-
6.
公开(公告)号:US20190067216A1
公开(公告)日:2019-02-28
申请号:US15691303
申请日:2017-08-30
Applicant: Micron Technology, Inc.
Inventor: Hongbin Zhu , Qinglin Zeng , Daniel Osterberg , Merri L. Carlson , Gordon A. Haller , Jeremy Adams
IPC: H01L23/58 , H01L23/528 , H01L23/522 , H01L23/00
CPC classification number: H01L23/585 , H01L23/5226 , H01L23/528 , H01L23/562
Abstract: A semiconductor device includes a semiconductor die comprising integrated circuitry over a substrate of a semiconductor material. A first die ring comprises one or more electrically conductive materials at least partially surrounding the integrated circuitry, the one or more electrically conductive materials comprising an electrically conductive path from proximate a surface of the substrate to an exposed surface of the semiconductor die. A second die ring comprises an electrically conductive material and is disposed around the first die ring. A first electrically conductive interconnect electrically connects the first die ring and to second die ring. Related semiconductor devices and semiconductor dice are disclosed.
-
-
-
-
-