Invention Application
- Patent Title: POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A POWER SEMICONDUCTOR PACKAGE
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Application No.: US17492865Application Date: 2021-10-04
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Publication No.: US20220115245A1Publication Date: 2022-04-14
- Inventor: Jayaganasan Narayanasamy , Syahir Abd Hamid , Meng How Chong , Michael Reyes Godoy , Chee Ming Lam , Adbul Rahman Mohamed , Sanjay Kumar Murugan , Thomas Stoek
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Priority: DE102020126857.2 20201013
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L23/495 ; H01L23/31

Abstract:
A method for fabricating a power semiconductor package includes: providing a leadframe having a die pad and a frame, wherein the die pad is connected to the frame by at least one tie bar; attaching a semiconductor die to the die pad; laser cutting through the at least one tie bar, thereby forming a cut surface; and after the laser cutting, molding over the die pad and the semiconductor die, wherein the cut surface is completely covered by molding compound.
Information query
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