公开(公告)号：US12068213B2

公开(公告)日：2024-08-20

申请号：US17531867

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Thai Kee Gan ,  Sanjay Kumar Murugan ,  Ralf Otremba

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/373 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/565 ,  H01L23/296 ,  H01L23/3121 ,  H01L23/373 ,  H01L23/4951 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/84 ,  H01L2224/3702

Abstract: A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

公开(公告)号：US20240145340A1

公开(公告)日：2024-05-02

申请号：US18406832

申请日：2024-01-08

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Angel Enverge ,  Chii Shang Hong ,  Chee Ming Lam ,  Sanjay Kumar Murugan ,  Subaramaniym Senivasan

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/4334 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/84 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/40175 ,  H01L2224/73263

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

公开(公告)号：US20220262693A1

公开(公告)日：2022-08-18

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US11908771B2

公开(公告)日：2024-02-20

申请号：US17524879

申请日：2021-11-12

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Angel Enverga ,  Chii Shang Hong ,  Chee Ming Lam ,  Sanjay Kumar Murugan ,  Subaramaniym Senivasan

IPC: H01L23/433 ,  H01L23/495 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4334 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/84 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/40175 ,  H01L2224/73263

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

公开(公告)号：US11362023B2

公开(公告)日：2022-06-14

申请号：US16510448

申请日：2019-07-12

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Meng How Chong ,  Elmer Senorin Holgado ,  Chee Ming Lam ,  Sanjay Kumar Murugan ,  Arivindran Navaretnasinggam ,  Kai Yang Tan ,  Lee Shuang Wang

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.

公开(公告)号：US10347554B2

公开(公告)日：2019-07-09

申请号：US15462858

申请日：2017-03-19

Applicant: Infineon Technologies AG

Inventor： Norbert Joson Santos ,  Edward Fuergut ,  Sanjay Kumar Murugan

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/40 ,  H01L23/367 ,  H01L23/495 ,  H01L21/56 ,  H01L21/02 ,  H01L21/67 ,  H01L33/48 ,  H01L33/54 ,  H01L33/62 ,  H01L33/64 ,  H01L21/3105 ,  H01L33/58 ,  H01L33/60 ,  H01L43/02 ,  H01L23/24

Abstract: An electronic component which comprises an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating at least part of at least one of the carrier and the electronic chip, and a functional structure covering a surface portion of the encapsulant, wherein at least part of the covered surface portion of the encapsulant is spatially selectively roughened.

公开(公告)号：US11621204B2

公开(公告)日：2023-04-04

申请号：US17177703

申请日：2021-02-17

Applicant: Infineon Technologies AG

Inventor： Oliver Markus Kreiter ,  Ludwig Busch ,  Angel Enverga ,  Mei Fen Hiew ,  Tian See Hoe ,  Elvis Keli ,  Kean Ming Koe ,  Sanjay Kumar Murugan ,  Michael Niendorf ,  Ivan Nikitin ,  Bernhard Stiller ,  Thomas Stoek ,  Ke Yan Tean

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

公开(公告)号：US20220173006A1

公开(公告)日：2022-06-02

申请号：US17531867

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Thai Kee Gan ,  Sanjay Kumar Murugan ,  Ralf Otremba

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

Abstract: A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.

公开(公告)号：US20230154827A1

公开(公告)日：2023-05-18

申请号：US17524879

申请日：2021-11-12

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Angel Enverga ,  Chii Shang Hong ,  Chee Ming Lam ,  Sanjay Kumar Murugan ,  Subaramaniym Senivasan

IPC: H01L23/433 ,  H01L23/495

CPC classification number: H01L23/4334 ,  H01L23/49568 ,  H01L24/40

Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.

公开(公告)号：US20220115245A1

公开(公告)日：2022-04-14

申请号：US17492865

申请日：2021-10-04

Applicant: Infineon Technologies AG

Inventor： Jayaganasan Narayanasamy ,  Syahir Abd Hamid ,  Meng How Chong ,  Michael Reyes Godoy ,  Chee Ming Lam ,  Adbul Rahman Mohamed ,  Sanjay Kumar Murugan ,  Thomas Stoek

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

Abstract: A method for fabricating a power semiconductor package includes: providing a leadframe having a die pad and a frame, wherein the die pad is connected to the frame by at least one tie bar; attaching a semiconductor die to the die pad; laser cutting through the at least one tie bar, thereby forming a cut surface; and after the laser cutting, molding over the die pad and the semiconductor die, wherein the cut surface is completely covered by molding compound.