Invention Application
- Patent Title: 3D Integrated Circuit and Methods of Forming the Same
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Application No.: US17697557Application Date: 2022-03-17
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Publication No.: US20220208607A1Publication Date: 2022-06-30
- Inventor: Hsun-Chung Kuang , Yen-Chang Chu , Cheng-Tai Hsiao , Ping-Yin Liu , Lan-Lin Chao , Yeur-Luen Tu , Chia-Shiung Tsai , Xiaomeng Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/00 ; H01L23/31 ; H01L25/04 ; H01L25/075 ; H01L23/538 ; H01L25/065 ; H01L23/29 ; H01L25/00

Abstract:
An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
Information query
IPC分类: