公开(公告)号：US11855109B2

公开(公告)日：2023-12-26

申请号：US17549501

申请日：2021-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chang Chu ,  Yeur-Luen Tu ,  Cheng-Yuan Tsai

IPC: H01L27/146

CPC classification number: H01L27/1462 ,  H01L27/1464 ,  H01L27/14607 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627

Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.

公开(公告)号：US20220310449A1

公开(公告)日：2022-09-29

申请号：US17842392

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/075 ,  H01L25/04 ,  H01L23/29 ,  H01L25/065

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US10967479B2

公开(公告)日：2021-04-06

申请号：US16439965

申请日：2019-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Liang ,  Hsun-Chung Kuang ,  Yen-Chang Chu

IPC: B24B37/04 ,  H01L21/304 ,  H01L21/321 ,  H01L21/3105

Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) pad, and an associated method to perform a CMP process. In some embodiments, the CMP pad comprises a polishing layer having a front surface with protruding asperities while a back surface being planar. A film electrode is attached to the back surface of the polishing layer and is isolated from the front surface of the polishing layer. The CMP pad further comprises an insulating layer covering sidewall and bottom surfaces of the film electrode.

公开(公告)号：US20210013098A1

公开(公告)日：2021-01-14

申请号：US17034526

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/04 ,  H01L25/075 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US11024774B2

公开(公告)日：2021-06-01

申请号：US16601822

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Wen Chang ,  Tzu-Chung Tsai ,  Yen-Chang Chu ,  Chia-Hua Lin

IPC: H01L33/40 ,  H01L51/52

Abstract: Various embodiments of the present disclosure are directed towards a display device. The display device includes an isolation structure disposed over a semiconductor substrate. An electrode is disposed at least partially over the isolation structure. A light-emitting structure is disposed over the electrode. A conductive reflector is disposed below the isolation structure and electrically coupled to the electrode. The conductive reflector is disposed at least partially between sidewalls of the light-emitting structure. The conductive reflector comprises a non-metal-doped aluminum material.

公开(公告)号：US10350726B2

公开(公告)日：2019-07-16

申请号：US15626612

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Liang ,  Hsun-Chung Kuang ,  Yen-Chang Chu

IPC: B24B37/04 ,  H01L21/304

Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) system, and an associated method to perform a CMP process. In some embodiments, the CMP system has a rotatable wafer carrier configured to hold a wafer face down to be processed. The CMP system also has a polishing layer attached to a polishing platen and having a front surface configured to interact with the wafer to be processed, and a CMP dispenser configured to dispense a slurry between an interface of the polishing layer and the wafer. The slurry contains charged abrasive particles therein. The CMP system also has a film electrode attached to a back surface of the polishing layer opposite to the front surface. The film electrode is configured to affect movements of the charged abrasive particles through applying an electrical field during the operation of the CMP system.

公开(公告)号：US20180158728A1

公开(公告)日：2018-06-07

申请号：US15423771

申请日：2017-02-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Chang Chu ,  Yao-Wen Chang ,  Sheng-Chau Chen ,  Alexander KALNITSKY

IPC: H01L21/768 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675

Abstract: A memory device includes a dielectric structure, a tungsten plug, a bottom electrode, a resistance switching element and a top electrode. The dielectric structure has an opening. The tungsten plug is embedded in the opening of the dielectric structure. The bottom electrode extends along top surfaces of the dielectric structure and the tungsten plug. The resistance switching element is present over the bottom electrode. The top electrode is present over the resistance switching element.

公开(公告)号：US20220208607A1

公开(公告)日：2022-06-30

申请号：US17697557

申请日：2022-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/04 ,  H01L25/075 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US20210151353A1

公开(公告)日：2021-05-20

申请号：US17140794

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Tai Hsiao ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/04 ,  H01L25/075 ,  H01L23/538 ,  H01L25/065 ,  H01L23/29 ,  H01L25/00

Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

公开(公告)号：US20180361529A1

公开(公告)日：2018-12-20

申请号：US15626612

申请日：2017-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Liang ,  Hsun-Chung Kuang ,  Yen-Chang Chu

IPC: B24B37/04 ,  H01L21/304

CPC classification number: B24B37/046 ,  B24B37/042 ,  H01L21/304 ,  H01L21/31053 ,  H01L21/3212

Abstract: The present disclosure relates to a chemical mechanical polishing (CMP) system, and an associated method to perform a CMP process. In some embodiments, the CMP system has a rotatable wafer carrier configured to hold a wafer face down to be processed. The CMP system also has a polishing layer attached to a polishing platen and having a front surface configured to interact with the wafer to be processed, and a CMP dispenser configured to dispense a slurry between an interface of the polishing layer and the wafer. The slurry contains charged abrasive particles therein. The CMP system also has a film electrode attached to a back surface of the polishing layer opposite to the front surface. The film electrode is configured to affect movements of the charged abrasive particles through applying an electrical field during the operation of the CMP system.