Invention Application
- Patent Title: Low-k Feature Formation Processes and Structures Formed Thereby
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Application No.: US17712561Application Date: 2022-04-04
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Publication No.: US20220230871A1Publication Date: 2022-07-21
- Inventor: Wan-Yi Kao , Chung-Chi Ko , Li Chun Te , Hsiang-Wei Lin , Te-En Cheng , Wei-Ken Lin , Guan-Yao Tu , Shu Ling Liao
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L21/311 ; H01L21/8234 ; H01L27/088 ; H01L29/66

Abstract:
Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.
Public/Granted literature
- US11705327B2 Low-k feature formation processes and structures formed thereby Public/Granted day:2023-07-18
Information query
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