公开(公告)号：US20190148514A1

公开(公告)日：2019-05-16

申请号：US15812966

申请日：2017-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L27/092

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US20240113202A1

公开(公告)日：2024-04-04

申请号：US18526084

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823814

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US11855182B2

公开(公告)日：2023-12-26

申请号：US17090121

申请日：2020-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Bo-Yu Lai ,  Li Chun Te ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Tien-I Bao ,  Wei-Ken Lin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66553 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/823814

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

公开(公告)号：US11417602B2

公开(公告)日：2022-08-16

申请号：US16919234

申请日：2020-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Cheng Shih ,  Chia Cheng Chou ,  Li Chun Te

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.

公开(公告)号：US11062901B2

公开(公告)日：2021-07-13

申请号：US16569791

申请日：2019-09-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia Cheng Chou ,  Po-Cheng Shih ,  Li Chun Te ,  Tien-I Bao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  C23C16/30 ,  H01L23/532 ,  H01L23/535

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

公开(公告)号：US20210202235A1

公开(公告)日：2021-07-01

申请号：US17201691

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US20210183646A1

公开(公告)日：2021-06-17

申请号：US17183807

申请日：2021-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia Cheng Chou ,  Po-Cheng Shih ,  Li Chun Te ,  Tien-I Bao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  C23C16/30 ,  H01L23/532 ,  H01L23/535

Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.

公开(公告)号：US20230326746A1

公开(公告)日：2023-10-12

申请号：US18326370

申请日：2023-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/3105 ,  H01L29/36 ,  H01L21/266 ,  H01L21/762

CPC classification number: H01L21/0228 ,  H01L27/0886 ,  H01L21/02211 ,  H01L21/823468 ,  H01L21/02208 ,  H01L21/02205 ,  H01L21/31111 ,  H01L21/02126 ,  H01L21/0214 ,  H01L29/6656 ,  H01L21/823431 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/3065 ,  H01L21/823437 ,  H01L29/66545 ,  H01L21/823481 ,  H01L21/31053 ,  H01L29/36 ,  H01L21/266 ,  H01L29/66795 ,  H01L21/76224

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such

公开(公告)号：US20220230871A1

公开(公告)日：2022-07-21

申请号：US17712561

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US10707165B2

公开(公告)日：2020-07-07

申请号：US15492243

申请日：2017-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Cheng Shih ,  Chia Cheng Chou ,  Li Chun Te

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522

Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.