公开(公告)号：US20230048536A1

公开(公告)日：2023-02-16

申请号：US17646770

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A method includes forming a first conductive feature in a first dielectric layer, forming a first metal cap over and contacting the first conductive feature, forming an etch stop layer over the first dielectric layer and the first metal cap, forming a second dielectric layer over the etch stop layer; and etching the second dielectric layer and the etch stop layer to form an opening. The first conductive feature is exposed to the opening. The method further includes selectively depositing a second metal cap at a bottom of the opening, forming an inhibitor film at the bottom of the opening and on the second metal cap, selectively depositing a conductive barrier in the opening, removing the inhibitor film, and filling remaining portions of the opening with a conductive material to form a second conductive feature.

公开(公告)号：US20230038952A1

公开(公告)日：2023-02-09

申请号：US17568984

申请日：2022-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L23/482 ,  H01L21/762

Abstract: A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.

公开(公告)号：US12249559B2

公开(公告)日：2025-03-11

申请号：US17568984

申请日：2022-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L23/482 ,  H01L21/762

Abstract: A device includes a first conductive feature in an insulating layer; a dielectric layer over the first conductive feature; a second conductive feature in the dielectric layer, wherein the second conductive feature is over and physically contacting the first conductive feature; an air spacer encircling the second conductive feature, wherein sidewalls of the second conductive feature are exposed to the air spacer; a metal cap covering the second conductive feature and extending over the air spacer, wherein the air spacer is sealed by a bottom surface of the metal cap; a first etch stop layer on the dielectric layer, wherein a sidewall of the first etch stop layer physically contacts a sidewall of the metal cap; and a second etch stop layer extending on a top surface of the metal cap and a top surface of the first etch stop layer.

公开(公告)号：US20210202235A1

公开(公告)日：2021-07-01

申请号：US17201691

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Chung-Chi Ko ,  Li Chun Te ,  Hsiang-Wei Lin ,  Te-En Cheng ,  Wei-Ken Lin ,  Guan-Yao Tu ,  Shu Ling Liao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088

Abstract: Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such features.

公开(公告)号：US10943868B2

公开(公告)日：2021-03-09

申请号：US16853136

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L21/67 ,  H01L21/764 ,  H01L23/522 ,  H01L21/3105 ,  H01L23/485 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor structure includes a first low-k dielectric layer disposed over a semiconductor substrate, a first conductive feature and a second conductive feature disposed in the first low-k dielectric layer, a second low-k dielectric layer disposed in the first low-k dielectric layer and interposed between the first conductive feature and the second conductive feature, where the second low-k dielectric layer includes an air gap, and an etch-stop layer disposed at an interface between the first low-k dielectric layer and the second low-k dielectric layer. The first low-k dielectric layer includes carbon whose concentration is graded in a direction away from the etch-stop layer.

公开(公告)号：US09741575B2

公开(公告)日：2017-08-22

申请号：US14202308

申请日：2014-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin ,  Chia-Ho Chen

IPC: C23C16/455 ,  H01L21/285

CPC classification number: H01L21/28506 ,  C23C16/45519 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/4558 ,  C23C16/45591

Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a gas delivery ring with an outlet disposed under the gas import. A pressure near the outlet of the gas delivery ring is smaller than that of the rest of the vacuum chamber.

公开(公告)号：US20200350417A1

公开(公告)日：2020-11-05

申请号：US16933276

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a fin extending from an upper surface of a substrate, a gate stack disposed over the fin, a first dielectric material disposed on a sidewall of the gate stack, an epitaxy region disposed adjacent the fin, a second dielectric material disposed on the epitaxy region and on a sidewall of the first dielectric material, wherein the second dielectric material has a greater thickness in a first portion over the epitaxy region than in a second portion over the epitaxy region disposed closer to the substrate than the first portion, a third dielectric material disposed on the second dielectric material, and a conductive feature extending through the third dielectric material and the second dielectric material to contact the epitaxy region.

公开(公告)号：US20200251418A1

公开(公告)日：2020-08-06

申请号：US16853136

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/535 ,  H01L23/522 ,  H01L23/00 ,  H01L23/485 ,  H01L21/67 ,  H01L21/3105 ,  H01L21/764 ,  H01L21/311 ,  H01L23/528

Abstract: A semiconductor structure includes a first low-k dielectric layer disposed over a semiconductor substrate, a first conductive feature and a second conductive feature disposed in the first low-k dielectric layer, a second low-k dielectric layer disposed in the first low-k dielectric layer and interposed between the first conductive feature and the second conductive feature, where the second low-k dielectric layer includes an air gap, and an etch-stop layer disposed at an interface between the first low-k dielectric layer and the second low-k dielectric layer. The first low-k dielectric layer includes carbon whose concentration is graded in a direction away from the etch-stop layer.

公开(公告)号：US10516035B2

公开(公告)日：2019-12-24

申请号：US15964366

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin ,  Chung-Chi Ko

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a fin structure over a substrate. The semiconductor device structure also includes a gate structure over the fin structure. The semiconductor device structure further includes a source/drain structure adjacent to the gate structure. In addition, the semiconductor device structure includes a first spacer layer between the gate structure and the source/drain structure, wherein the first spacer layer has a protruding portion extending towards the substrate.

公开(公告)号：US20180158726A1

公开(公告)日：2018-06-07

申请号：US15888130

申请日：2018-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/764 ,  H01L21/67

CPC classification number: H01L21/76825 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/67115 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure includes a first dielectric layer disposed over a substrate; a first metal feature and a second metal feature embedded in the first dielectric layer and spaced from each other; an etch stop layer disposed between the first and second metal features and on sidewalls of the first dielectric layer; a second dielectric layer disposed over the etch stop layer and between the first and second metal features; and an air gap surrounded by the second dielectric layer and disposed between the first and second metal features.