Invention Application
- Patent Title: MULTICORE BUS ARCHITECTURE WITH WIRE REDUCTION AND PHYSICAL CONGESTION MINIMIZATION VIA SHARED TRANSACTION CHANNELS
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Application No.: US17735255Application Date: 2022-05-03
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Publication No.: US20220261373A1Publication Date: 2022-08-18
- Inventor: David M. Thompson , Timothy Anderson , Joseph Zbiciak , Abhijeet A. Chachad , Kai Chirca , Matthew D. Pierson
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Main IPC: G06F13/42
- IPC: G06F13/42 ; G06F13/362

Abstract:
The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.
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