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公开(公告)号：US11501024B2
公开(公告)日：2022-11-15
申请号：US16047298
申请日：2018-07-27
IPC分类号： G06F21/78 , G06F12/0815 , G06F21/79 , G06F12/14 , G06F12/0817 , G06F13/16 , G06F13/30 , G06F12/0831 , H04L9/40 , G06F13/42 , G06F12/1081 , G06F13/28 , G06F13/40 , G06F12/0842
摘要： Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.
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2.发明申请公开(公告)号：US20190354500A1
公开(公告)日：2019-11-21
申请号：US16430748
申请日：2019-06-04
发明人： David M. Thompson , Timothy D. Anderson , Joseph R.M. Zbiciak , Abhijeet A. Chachad , Kai Chirca , Matthew D. Pierson
IPC分类号： G06F13/40 , G06F13/42 , H04L12/801 , G06F13/364 , H04L12/819
摘要： This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
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公开(公告)号：US20190146790A1
公开(公告)日：2019-05-16
申请号：US16227238
申请日：2018-12-20
发明人： Timothy D. Anderson , Joseph Zbiciak , Duc Quang Bui , Abhijeet Chachad , Kai Chirca , Naveen Bhoria , Matthew D. Pierson , Daniel Wu , Ramakrishnan Venkatasubramanian
IPC分类号： G06F9/30 , G06F9/345 , G06F9/38 , G06F11/10 , G06F9/32 , G06F12/0875 , G06F12/0897 , G06F11/00
摘要： Disclosed embodiments include a data processing apparatus having a processing core, a memory, and a streaming engine. The streaming engine is configured to receive a plurality of data elements stored in the memory and to provide the plurality of data elements as a data stream to the processing core, and includes an address generator to generate addresses corresponding to locations in the memory, a buffer to store the data elements received from the locations in the memory corresponding to the generated addresses, and an output to supply the data elements received from the memory to the processing core as the data stream.
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公开(公告)号：US09652404B2
公开(公告)日：2017-05-16
申请号：US15047318
申请日：2016-02-18
发明人： Matthew D. Pierson , Kai Chirca
IPC分类号： G06F12/00 , G06F12/1081 , G06F12/0815 , G06F12/0831 , G06F13/16 , H04L29/06 , G06F13/42 , G06F12/0817 , G06F13/28 , G06F13/40 , G06F12/0842 , G06F13/00
CPC分类号： G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
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公开(公告)号：US20140156951A1
公开(公告)日：2014-06-05
申请号：US14060192
申请日：2013-10-22
发明人： Matthew D. Pierson , Kai Chirca
IPC分类号： G06F12/08
CPC分类号： G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.
摘要翻译： 本发明优化了非共享访问，避免了相干端点之间的依赖关系，即使在共享时也能确保系统的带宽。 相干控制器分布在所有相干端点上。 每个存储器端点的相干控制器保持每个相干访问的状态，以确保事件的正确排序。 本发明的一致性控制器使用先入先出分配来确保资源的充分利用在停止和简单实现之前。 相干控制器提供每个内存端点的Snoop命令/响应ID分配。
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公开(公告)号：US20140115272A1
公开(公告)日：2014-04-24
申请号：US14059732
申请日：2013-10-22
发明人： Matthew D. Pierson , Daniel B. Wu , Kai Chirca
IPC分类号： G06F12/08
CPC分类号： G06F21/78 , G06F12/0815 , G06F12/0828 , G06F12/0831 , G06F12/0835 , G06F12/0842 , G06F12/1081 , G06F12/1458 , G06F12/1491 , G06F13/1626 , G06F13/1663 , G06F13/287 , G06F13/4022 , G06F13/42 , G06F21/79 , G06F2212/1032 , G06F2212/283 , G06F2212/62 , G06F2212/621 , H04L63/0263 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： This invention mitigates these deadlocking issues by a adding a separate non-blocking pipeline for snoop returns. This separate pipeline would not be blocked behind coherent requests. This invention also repartitions the master initiated traffic to move cache evictions (both with and without data) and non-coherent writes to the new non-blocking channel. This non-blocking pipeline removes the need for any coherent requests to complete before the snoop request can reach the memory controller. Repartitioning cache initiated evictions to the non-blocking pipeline prevents deadlock when snoop and eviction occur concurrently. The non-blocking channel of this invention combines snoop responses from memory controller initiated requests and master initiated evictions/non-coherent writes.
摘要翻译： 本发明通过为窥探返回添加单独的非阻塞管道来缓解这些死锁问题。 这个单独的管道不会被阻塞在一致的请求之后。 本发明还重新分配主发起的流量以移动高速缓存驱逐（包括和不具有数据）和非相干写入到新的非阻塞信道。 这种非阻塞管道消除了在侦听请求到达内存控制器之前需要完成的任何一致的请求。 重新分区高速缓存启动的撤回到非阻塞管道可以同时发生侦听和撤离时防止死锁。 本发明的非阻塞信道组合来自存储器控制器发起的请求和主发起的驱逐/非相干写入的窥探响应。
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公开(公告)号：US11789872B2
公开(公告)日：2023-10-17
申请号：US17384864
申请日：2021-07-26
IPC分类号： G06F12/08 , G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F12/0886 , G06F9/38
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0862 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F12/0886 , G06F2212/602 , G06F2212/6022 , G06F2212/6028 , Y02D10/00
摘要： A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
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公开(公告)号：US20230048071A1
公开(公告)日：2023-02-16
申请号：US17971691
申请日：2022-10-24
IPC分类号： G06F21/78 , G06F12/0815 , G06F21/79 , G06F12/14 , G06F12/0817 , G06F13/16 , G06F13/30 , G06F12/0831 , H04L9/40 , G06F13/42 , G06F12/1081 , G06F13/28 , G06F13/40 , G06F12/0842
摘要： Disclosed embodiments relate to a security firewall having a security hierarchy including: secure master (SM); secure guest (SG); and non-secure (NS). There is one secure master and n secure guests. The firewall includes one secure region for secure master and one secure region for secure guests. The SM region only allows access from the secure master and the SG region allows accesses from any secure transaction. Finally, the non-secure region can be implemented two ways. In a first option, non-secure regions may be accessed only upon non-secure transactions. In a second option, non-secure regions may be accessed any processing core. In this second option, the access is downgraded to a non-secure access if the security identity is secure master or secure guest. If the two security levels are not needed the secure master can unlock the SM region to allow any secure guest access to the SM region.
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公开(公告)号：US20210011872A1
公开(公告)日：2021-01-14
申请号：US17030518
申请日：2020-09-24
发明人： David M. Thompson , Timothy D. Anderson , Joseph R.M. Zbiciak , Abhijeet A. Chachad , Kai Chirca , Matthew D. Pierson
IPC分类号： G06F13/40 , G06F13/364 , G06F13/42 , H04L12/819 , H04L12/801
摘要： This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
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公开(公告)号：US10311007B2
公开(公告)日：2019-06-04
申请号：US15903183
申请日：2018-02-23
发明人： David M. Thompson , Timothy D. Anderson , Joseph R. M. Zbiciak , Abhijeet A. Chachad , Kai Chirca , Matthew D. Pierson
IPC分类号： G06F13/40 , G06F13/42 , H04L12/801 , G06F13/364 , H04L12/819
摘要： This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.
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