Invention Application
- Patent Title: RECALIBRATION OF PHY CIRCUITRY FOR THE PCI EXPRESS (PIPE) INTERFACE BASED ON USING A MESSAGE BUS INTERFACE
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Application No.: US17738625Application Date: 2022-05-06
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Publication No.: US20220269641A1Publication Date: 2022-08-25
- Inventor: Michelle C. Jen , Minxi Gao , Debendra Das Sharma , Fulvio Spagna , Bruce A. Tennant , Noam Dolev Geldbard
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F13/42
- IPC: G06F13/42

Abstract:
An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.
Public/Granted literature
- US11789892B2 Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface Public/Granted day:2023-10-17
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