公开(公告)号：US11729096B2

公开(公告)日：2023-08-15

申请号：US17391557

申请日：2021-08-02

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Mark S. Myers ,  Don Soltis ,  Ramacharan Sundararaman ,  Stephen R. Van Doren ,  Mahesh Wagh

IPC分类号： H04L45/52 ,  H04L69/18 ,  H04L49/60 ,  H04L69/323

CPC分类号： H04L45/52 ,  H04L49/60 ,  H04L69/18 ,  H04L69/323

摘要： Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US20180067855A1

公开(公告)日：2018-03-08

申请号：US15665541

申请日：2017-08-01

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC分类号： G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

摘要： A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US09720838B2

公开(公告)日：2017-08-01

申请号：US14670578

申请日：2015-03-27

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC分类号： G06F12/00 ,  G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

摘要： A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

公开(公告)号：US20160283303A1

公开(公告)日：2016-09-29

申请号：US14671881

申请日：2015-03-27

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen

IPC分类号： G06F11/07 ,  G06F3/06

CPC分类号： G06F11/079 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/0793

摘要： A shared memory controller receives a memory access request from a computing node, the request corresponding to a particular line of pooled memory. An error corresponding to the request is identified and the request is forwarded to a second shared memory controller in response to the error. A response is received to the request from the second shared memory controller. The response can be forwarded to the computing node by the shared memory controller.

摘要翻译： 共享存储器控制器从计算节点接收存储器访问请求，该请求对应于合并存储器的特定行。 识别与该请求相对应的错误，并且响应于该错误将该请求转发到第二共享存储器控制器。 接收到来自第二共享存储器控制器的请求的响应。 响应可以由共享存储器控制器转发到计算节点。

公开(公告)号：US20160179710A1

公开(公告)日：2016-06-23

申请号：US14580918

申请日：2014-12-23

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Daniel S. Froelich ,  Venkatraman Iyer ,  Michelle C. Jen ,  Rahul R. Shah ,  Eric M. Lee

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F13/4068 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4282

摘要： An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.

摘要翻译： 提供了一种包括用于串行互连的物理接口的装置。 物理接口包括缓冲器，其可选择用作缓冲器控制线上的电压电平的漂移缓冲器或弹性缓冲器。 物理接口还包括可由逻辑控制线上的电压电平启用或禁用的编码逻辑。 此外，物理接口还包括可以通过通信控制线上的电压电平启用或禁用的有序集发生器。

公开(公告)号：US20240160585A1

公开(公告)日：2024-05-16

申请号：US18419159

申请日：2024-01-22

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC分类号： G06F13/16 ,  G06F12/14 ,  G06F13/38 ,  G06F13/42

CPC分类号： G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/00

摘要： A first die has a port to couple the first die to a second die over a die-to-die interconnect. The port includes circuitry to implement a physical layer of the die-to-die interconnect, send first protocol identification data over the physical layer to identify a first protocol in a plurality of protocols, send first data over the interconnect to the second die, wherein the first data comprise data of the first protocol, send second protocol identification data over the physical layer to identify a different second protocol in the plurality of protocols, and send second data over the interconnect to the second die, wherein the second data comprise flits of the second protocol.

公开(公告)号：US20240012759A1

公开(公告)日：2024-01-11

申请号：US18462561

申请日：2023-09-07

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC分类号： G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

CPC分类号： G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F13/1673 ,  G06F13/4282 ,  G06F12/0806 ,  G06F12/0808 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/1016

摘要： A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US20210240623A1

公开(公告)日：2021-08-05

申请号：US17236692

申请日：2021-04-21

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC分类号： G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

摘要： A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US10713209B2

公开(公告)日：2020-07-14

申请号：US16446470

申请日：2019-06-19

申请人： Intel Corporation

发明人： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

IPC分类号： G06F13/00 ,  G06F13/42

摘要： An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

公开(公告)号：US20170004098A1

公开(公告)日：2017-01-05

申请号：US15039468

申请日：2013-12-26

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC分类号： G06F13/16 ,  G06F13/42 ,  G06F12/14

CPC分类号： G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

摘要： A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

摘要翻译： 共享存储器控制器用于通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。 要允许多个独立节点中的每一个访问共享存储器资源的相应部分。 在数据链路上发送互连协议数据和存储器访问协议数据，可以定义和识别互连协议数据和存储器访问协议数据之间的转换。