Examples described herein relate to a packet processing device. In some examples, the packet processing device includes multiple processors and data plane circuitry. In some examples, a first processor of the multiple processors is to perform a first control plane, a second processor of the multiple processors is to perform a second control plane, and the first and second control planes are to communicate through an interface and wherein the first control plane is to discover capabilities of data plane circuitry and configure operation of the data plane circuitry by the interface.