公开(公告)号：US20220276809A1

公开(公告)日：2022-09-01

申请号：US17747955

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Keren GUY ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Kirill KAZATSKER ,  Arunkumar BALAKRISHNAN ,  Jayaprakash SHANMUGAM ,  Hieu TRAN

IPC: G06F3/06

Abstract: Examples described herein relate to a packet processing device. In some examples, the packet processing device includes multiple processors and data plane circuitry. In some examples, a first processor of the multiple processors is to perform a first control plane, a second processor of the multiple processors is to perform a second control plane, and the first and second control planes are to communicate through an interface and wherein the first control plane is to discover capabilities of data plane circuitry and configure operation of the data plane circuitry by the interface.

公开(公告)号：US20230259352A1

公开(公告)日：2023-08-17

申请号：US18135566

申请日：2023-04-17

Applicant: Intel Corporation

Inventor： Kirill KAZATSKER ,  Keren GUY ,  Anjali Singhai JAIN ,  Matthew VICK ,  Jayaprakash SHANMUGAM

IPC: G06F8/65 ,  H04L67/00 ,  G06F21/51 ,  G06F21/57

CPC classification number: G06F8/65 ,  H04L67/34 ,  G06F21/51 ,  G06F21/57

Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a network interface device that includes a network interface, a host interface, and multiple processors. In some examples, a first processor of the multiple processors is to execute a first control plane process and an embedded software update is to occur by: installation and execution of a second control plane process on the first processor and a third control plane process is to cause utilization of the second control plane process.

公开(公告)号：US20220166666A1

公开(公告)日：2022-05-26

申请号：US17670355

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Anjali Singhai JAIN ,  Keren GUY ,  Jayaprakash SHANMUGAM ,  Neerav PARIKH ,  Daniel DALY ,  Arunkumar BALAKRISHNAN

IPC: H04L41/0803

Abstract: Examples described herein relate to a packet processing device that includes circuitry to perform packet processing operations according to a configuration and circuitry to execute control plane software to provide the configuration to the circuitry to perform packet processing operations according to the configuration. In some examples, the circuitry to perform packet processing operations according to the configuration is to continue operation independent of operation of the circuitry to execute control plane software.