公开(公告)号：US20220166666A1

公开(公告)日：2022-05-26

申请号：US17670355

申请日：2022-02-11

Applicant: Intel Corporation

Inventor： Anjali Singhai JAIN ,  Keren GUY ,  Jayaprakash SHANMUGAM ,  Neerav PARIKH ,  Daniel DALY ,  Arunkumar BALAKRISHNAN

IPC: H04L41/0803

Abstract: Examples described herein relate to a packet processing device that includes circuitry to perform packet processing operations according to a configuration and circuitry to execute control plane software to provide the configuration to the circuitry to perform packet processing operations according to the configuration. In some examples, the circuitry to perform packet processing operations according to the configuration is to continue operation independent of operation of the circuitry to execute control plane software.

公开(公告)号：US20240031289A1

公开(公告)日：2024-01-25

申请号：US18375480

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Arunkumar BALAKRISHNAN ,  Anurag AGRAWAL ,  Elazar COHEN ,  Anjali Singhai JAIN

IPC: H04L45/748 ,  H04L45/00 ,  H04L12/46

CPC classification number: H04L45/748 ,  H04L45/566 ,  H04L12/4633

Abstract: Examples described herein relate to a network interface device. The network interface device can include circuitry that is to: perform a route lookup for a packet based on first and second lookup operations, wherein the first lookup operation comprises a longest prefix match (LPM) to output a route identifier based on a destination Internet Protocol (IP) address of the packet and wherein the second look up operation comprises an exact match operation to determine an action based on the route identifier and a packet header.

公开(公告)号：US20240396844A1

公开(公告)日：2024-11-28

申请号：US18789463

申请日：2024-07-30

Applicant: Intel Corporation

Inventor： Shweta SHRIVASTAVA ,  Nupur JAIN ,  Arunkumar BALAKRISHNAN ,  John Andrew FINGERHUT ,  Neelakanta Venkatesh PETLA ,  Vishalakshi R

IPC: H04L47/20 ,  H04L45/74

Abstract: Examples described herein relate to a network interface device comprising: an interface to a port; and circuitry to: perform parallel evaluation of multiple rules for a packet; drop the packet based at least in part on an indication by the parallel evaluation that communication with a target is not permitted; and permit communication of the packet based at least in part on a second indication by the parallel evaluation that communication with the target is permitted. In some examples, the parallel evaluation of multiple rules is to evaluate one or more of: a permitted sender Internet Protocol (IP) address range, a permitted destination IP address range, a permitted packet protocol, or a permitted egress port range.

公开(公告)号：US20220276809A1

公开(公告)日：2022-09-01

申请号：US17747955

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Keren GUY ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Kirill KAZATSKER ,  Arunkumar BALAKRISHNAN ,  Jayaprakash SHANMUGAM ,  Hieu TRAN

IPC: G06F3/06

Abstract: Examples described herein relate to a packet processing device. In some examples, the packet processing device includes multiple processors and data plane circuitry. In some examples, a first processor of the multiple processors is to perform a first control plane, a second processor of the multiple processors is to perform a second control plane, and the first and second control planes are to communicate through an interface and wherein the first control plane is to discover capabilities of data plane circuitry and configure operation of the data plane circuitry by the interface.