公开(公告)号：US20250141794A1

公开(公告)日：2025-05-01

申请号：US18518814

申请日：2023-11-24

Applicant: Intel Corporation

Inventor： Xiao WANG ,  Sridhar SAMUDRALA ,  Zhirun YAN ,  Ji LI ,  Mohammad Abdul AWAL ,  Qi ZHANG ,  Ping YU ,  Yadong LI ,  Hieu TRAN ,  Jayaprakash SHANMUGAM

IPC: H04L45/00 ,  H04L45/42 ,  H04L45/741

Abstract: Examples described herein relate to a network interface device. In some examples, the network interface device includes a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry. The circuitry can be configured to: apply, for a tunnel packet, a single match-action rule that comprises a value of the encapsulation header of the tunnel packet and a value of the encapsulated header, wherein the single match-action rule is based on two or more match-action rules.

公开(公告)号：US20220276809A1

公开(公告)日：2022-09-01

申请号：US17747955

申请日：2022-05-18

Applicant: Intel Corporation

Inventor： Keren GUY ,  Anjali Singhai JAIN ,  Neerav PARIKH ,  Kirill KAZATSKER ,  Arunkumar BALAKRISHNAN ,  Jayaprakash SHANMUGAM ,  Hieu TRAN

IPC: G06F3/06

Abstract: Examples described herein relate to a packet processing device. In some examples, the packet processing device includes multiple processors and data plane circuitry. In some examples, a first processor of the multiple processors is to perform a first control plane, a second processor of the multiple processors is to perform a second control plane, and the first and second control planes are to communicate through an interface and wherein the first control plane is to discover capabilities of data plane circuitry and configure operation of the data plane circuitry by the interface.