Invention Application
- Patent Title: VOLTAGE CALIBRATION SCANS TO REDUCE MEMORY DEVICE OVERHEAD
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Application No.: US17198755Application Date: 2021-03-11
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Publication No.: US20220293208A1Publication Date: 2022-09-15
- Inventor: Kishore Kumar MUCHHERLA , Mustafa N. KAYNAK , Sivagnanam PARTHASARATHY , Xiangang LUO , Peter FEELEY , Devin M. BATUTIS , Jiangang WU , Sampath K RATNAM , Shane NOWELL , Karl D. Schuh
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee: MICRON TECHNOLOGY, INC.
- Current Assignee Address: US ID Boise
- Main IPC: G11C29/50
- IPC: G11C29/50 ; G06F12/02 ; G11C7/10 ; G11C29/02 ; G11C16/26

Abstract:
A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.
Public/Granted literature
- US11587639B2 Voltage calibration scans to reduce memory device overhead Public/Granted day:2023-02-21
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