公开(公告)号：US20230012978A1

公开(公告)日：2023-01-19

申请号：US17946328

申请日：2022-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qisong LIN ,  Vamsi Pavan RAYAPROLU ,  Jiangang WU ,  Sampath K. RATNAM ,  Sivagnanam PARTHASARATHY ,  Shao Chun SHI

IPC: G06F11/07

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.

公开(公告)号：US20220321148A1

公开(公告)日：2022-10-06

申请号：US17223910

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Sivagnanam PARTHASARATHY

IPC: H03M13/37 ,  G06F11/10

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.

公开(公告)号：US20240168847A1

公开(公告)日：2024-05-23

申请号：US18507805

申请日：2023-11-13

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Eyal EN GAD ,  Zhengang CHEN ,  Sivagnanam PARTHASARATHY ,  Phong Sy NGUYEN ,  Dung V. NGUYEN

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1016

Abstract: A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.

公开(公告)号：US20230044471A1

公开(公告)日：2023-02-09

申请号：US17397707

申请日：2021-08-09

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Sivagnanam PARTHASARATHY

IPC: H03M13/11 ,  H03M13/09 ,  H03K19/17728

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Energy function values are determined for bits of the codeword based on soft information for the bits of the codeword. A bit of the codeword is flipped when the energy function values for a bit of the codeword satisfies a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

公开(公告)号：US20220383955A1

公开(公告)日：2022-12-01

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar MUCHHERLA ,  Sampath K. RATNAM ,  Shane NOWELL ,  Sivagnanam PARTHASARATHY ,  Mustafa N. KAYNAK ,  Karl D. SCHUH ,  Peter FEELEY ,  Jiangang WU

IPC: G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

公开(公告)号：US20230315570A1

公开(公告)日：2023-10-05

申请号：US18329886

申请日：2023-06-06

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Patrick R. KHAYAT ,  Sivagnanam PARTHASARATHY

IPC: G06F11/10

CPC classification number: G06F11/1076

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.

公开(公告)号：US20220350700A1

公开(公告)日：2022-11-03

申请号：US17246509

申请日：2021-04-30

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Patrick R. KHAYAT ,  Sivagnanam PARTHASARATHY

IPC: G06F11/10

Abstract: Methods, systems, and apparatus for error correction with syndrome computation in a memory device are described. A first syndrome for first encoded data is generated in a memory device. The first syndrome and the first encoded data are transmitted to a controller that is coupled with the memory device. A second syndrome for first and second encoded data is generated. The first encoded data and the second encoded data are interrelated according to an error correction code. The second syndrome is transmitted to the controller without the second encoded data and the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.

公开(公告)号：US20220321144A1

公开(公告)日：2022-10-06

申请号：US17223804

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Sivagnanam PARTHASARATHY

IPC: H03M13/11 ,  H03M13/15 ,  H03M13/29 ,  H03M13/43

Abstract: Methods, systems, and apparatuses for stall mitigation in iterative decoders are described. A codeword is received from a memory device. The codeword is iteratively error corrected based on a first bit flipping criterion. A stall condition in the multiple error correction iterations is detected. In response to the detection, the codeword is error corrected based on a second bit flipping criterion that is different from the first bit flipping criterion.

公开(公告)号：US20220416815A1

公开(公告)日：2022-12-29

申请号：US17899495

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Mustafa N. KAYNAK ,  Sivagnanam PARTHASARATHY

IPC: H03M13/37 ,  G06F11/10

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword is error corrected for a first number of iterations. The error correction includes traversing the codeword according to a first order. The codeword is error corrected for a second number of the iterations. The error correction of the codeword during a second iteration from the second number of iterations includes traversing the codeword according to a second order that is different from the first order.

公开(公告)号：US20220293208A1

公开(公告)日：2022-09-15

申请号：US17198755

申请日：2021-03-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar MUCHHERLA ,  Mustafa N. KAYNAK ,  Sivagnanam PARTHASARATHY ,  Xiangang LUO ,  Peter FEELEY ,  Devin M. BATUTIS ,  Jiangang WU ,  Sampath K RATNAM ,  Shane NOWELL ,  Karl D. Schuh

IPC: G11C29/50 ,  G06F12/02 ,  G11C7/10 ,  G11C29/02 ,  G11C16/26

Abstract: A voltage calibration scan is initiated. A first value of a data state metric measured for a sample block of a memory device based on associated with a first bin of blocks designated as a current is received. The first value is designated as a minimum value. A second value of the data state metric for the sample block is measured based on a set of read voltage offsets associated with a second bin of blocks having an index value higher than the current bin. In response to determining that the second value exceeds the first value, the first bin is maintained as the current bin and the voltage calibration scan is stopped.