Invention Application
- Patent Title: Package Component with Stepped Passivation Layer
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Application No.: US17809960Application Date: 2022-06-30
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Publication No.: US20220336276A1Publication Date: 2022-10-20
- Inventor: Ming-Da Cheng , Tzy-Kuang Lee , Song-Bor Lee , Wen-Hsiung Lu , Po-Hao Tsai , Wen-Che Chang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/00

Abstract:
A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
Public/Granted literature
- US11961762B2 Package component with stepped passivation layer Public/Granted day:2024-04-16
Information query
IPC分类: