公开(公告)号：US09412671B1

公开(公告)日：2016-08-09

申请号：US14700557

申请日：2015-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsien-Chie Tsai ,  Chang-Sheng Lee ,  Fu-Yuan Chang ,  Hung-Yin Lin ,  Wen-Che Chang ,  Chien-Pin Hsu

IPC: H01L21/66 ,  H01L21/30 ,  H01L21/3065 ,  H01L21/324

CPC classification number: H01L21/324 ,  H01L21/67017 ,  H01L21/67109 ,  H01L21/67248

Abstract: A method for controlling processing temperature in semiconductor fabrication is provided. The method includes detecting temperature in a first chamber configured to process a semiconductor wafer. The method further includes creating a flow of heat-exchange medium in a second chamber which is connected to the first chamber to cool the first chamber. The method also includes controlling the flow of heat-exchange medium according to the temperature detected in the first chamber by changing a covered area of a first ventilation unit which allows the entry of the heat-exchange medium to the second chamber.

Abstract translation: 提供了一种用于控制半导体制造中的处理温度的方法。 该方法包括检测构造成处理半导体晶片的第一室中的温度。 该方法还包括在连接到第一室以冷却第一室的第二室中产生热交换介质流。 该方法还包括通过改变允许热交换介质进入第二室的第一通风单元的覆盖区域，根据第一室中检测到的温度来控制热交换介质的流动。

公开(公告)号：US11450567B2

公开(公告)日：2022-09-20

申请号：US17085731

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US20240222194A1

公开(公告)日：2024-07-04

申请号：US18604691

申请日：2024-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US11961762B2

公开(公告)日：2024-04-16

申请号：US17809960

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US20220336276A1

公开(公告)日：2022-10-20

申请号：US17809960

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.

公开(公告)号：US20210375675A1

公开(公告)日：2021-12-02

申请号：US17085731

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Tzy-Kuang Lee ,  Song-Bor Lee ,  Wen-Hsiung Lu ,  Po-Hao Tsai ,  Wen-Che Chang

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.