A method includes forming a stack of multi-layers, each multi-layer including a first isolation layer, a semiconductor layer, and a first metal layer; etching the stack of multi-layers to form gate trenches in a channel region; removing the first isolation layers and the first metal layers from the channel region, resulting in channel portions of the semiconductor layers exposed in the gate trenches; laterally recessing the first metal layers from the gate trenches, resulting in gaps between adjacent layers of the first isolation layers and the semiconductor layers; forming an inner spacer layer in the gaps; forming a ferroelectric (FE) layer surrounding each of the channel portions and over sidewalls of the gate trenches, wherein the inner spacer layer is disposed laterally between the FE layer and the first metal layers; and depositing a metal gate layer over the FE layer and filling the gate trenches.