Invention Application
- Patent Title: Warpage Control in the Packaging of Integrated Circuits
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Application No.: US17869384Application Date: 2022-07-20
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Publication No.: US20220361293A1Publication Date: 2022-11-10
- Inventor: Ming-Da Cheng , Hsiu-Jen Lin , Cheng-Ting Chen , Wei-Yu Chen , Chien-Wei Lee , Chung-Shi Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H05B3/02
- IPC: H05B3/02 ; H01L21/677 ; H01L23/00 ; H01L21/68 ; H01L21/683 ; B23K3/08

Abstract:
A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.
Public/Granted literature
- US12144065B2 Warpage control in the packaging of integrated circuits Public/Granted day:2024-11-12
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