公开(公告)号：US12144065B2

公开(公告)日：2024-11-12

申请号：US17869384

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: B23K3/08 ,  H01L21/677 ,  H01L21/68 ,  H01L21/683 ,  H01L23/00 ,  H05B3/02 ,  B23K101/40

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

公开(公告)号：US20240153842A1

公开(公告)日：2024-05-09

申请号：US18404504

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2924/15311

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US11901258B2

公开(公告)日：2024-02-13

申请号：US17227790

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L23/50 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US10535644B1

公开(公告)日：2020-01-14

申请号：US16059052

申请日：2018-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Ting Kuo ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Hao-Jan Pei ,  Yu-Peng Tsai ,  Chia-Lun Chang ,  Chih-Chiang Tsao ,  Philip Yu-shuan Chung

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L27/06 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522 ,  H01L21/683

Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.

公开(公告)号：US20200006308A1

公开(公告)日：2020-01-02

申请号：US16059052

申请日：2018-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Ting Kuo ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Hao-Jan Pei ,  Yu-Peng Tsai ,  Chia-Lun Chang ,  Chih-Chiang Tsao ,  Philip Yu-shuan Chung

IPC: H01L25/00 ,  H01L23/31 ,  H01L27/06 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.

公开(公告)号：US11342321B2

公开(公告)日：2022-05-24

申请号：US16740463

申请日：2020-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsuan-Ting Kuo ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Hao-Jan Pei ,  Yu-Peng Tsai ,  Chia-Lun Chang ,  Chih-Chiang Tsao ,  Philip Yu-Shuan Chung

IPC: H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L27/06 ,  H01L23/522

Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.

公开(公告)号：US11002927B2

公开(公告)日：2021-05-11

申请号：US16281090

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Lun Chang ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Hsuan-Ting Kuo ,  Chia-Shen Cheng ,  Chih-Chiang Tsao

IPC: G02B6/42 ,  H01L21/683 ,  H01L21/56 ,  G02B6/43 ,  H01L23/538 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18 ,  H05K1/02

Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.

公开(公告)号：US10903090B2

公开(公告)日：2021-01-26

申请号：US16414763

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chen ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Lun Chang ,  Chia-Shen Cheng ,  Cheng-Shiuan Wong

IPC: H01L21/02 ,  H01L21/56 ,  H01L21/78 ,  H01L23/28 ,  H01L23/544

Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.

公开(公告)号：US20200271873A1

公开(公告)日：2020-08-27

申请号：US16281090

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Lun Chang ,  Ching-Hua Hsieh ,  Cheng-Ting Chen ,  Hsiu-Jen Lin ,  Hsuan-Ting Kuo ,  Chia-Shen Cheng ,  Chih-Chiang Tsao

IPC: G02B6/42 ,  H05K1/02 ,  H01L23/538 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  G02B6/43 ,  H05K1/18

Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.

公开(公告)号：US20220361293A1

公开(公告)日：2022-11-10

申请号：US17869384

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: H05B3/02 ,  H01L21/677 ,  H01L23/00 ,  H01L21/68 ,  H01L21/683 ,  B23K3/08

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.