Invention Application
- Patent Title: ACCESSING ERROR STATISTICS FROM DRAM MEMORIES HAVING INTEGRATED ERROR CORRECTION
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Application No.: US17878149Application Date: 2022-08-01
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Publication No.: US20220365849A1Publication Date: 2022-11-17
- Inventor: Siva Srinivas Kothamasu
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F13/16 ; G11C29/52
Abstract:
In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.
Public/Granted literature
- US11714713B2 Accessing error statistics from dram memories having integrated error correction Public/Granted day:2023-08-01
Information query
