A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.