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    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT
    3.
    发明公开
    MEMORY DEVICE INCLUDING PASS TRANSISTOR CIRCUIT 审中-公开

    公开(公告)号：US20240105268A1

    公开(公告)日：2024-03-28

    申请号：US18529897

    申请日：2023-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

    IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

    CPC classification number: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H10B41/27 ,  H10B43/27

    Abstract: A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    Memory device including pass transistor circuit
    5.
    发明授权
    Memory device including pass transistor circuit 有权

    公开(公告)号：US11462275B2

    公开(公告)日：2022-10-04

    申请号：US17227501

    申请日：2021-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungyeon Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Hongsoo Jeon

    IPC: G11C16/24 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582

    Abstract: A memory device includes; a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.

    Memory device having row decoder array architecture
    6.
    发明授权
    Memory device having row decoder array architecture 有权

    公开(公告)号：US12198753B2

    公开(公告)日：2025-01-14

    申请号：US17953715

    申请日：2022-09-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungyeon Kim ,  Jooyong Park ,  Hongsoo Jeon

    IPC: G11C7/02 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/4099

    Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.

    NONVOLATILE MEMORY DEVICES AND MEMORY PACKAGES INCLUDING THE SAME
    7.
    发明申请
    NONVOLATILE MEMORY DEVICES AND MEMORY PACKAGES INCLUDING THE SAME 有权

    公开(公告)号：US20250014645A1

    公开(公告)日：2025-01-09

    申请号：US18443463

    申请日：2024-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Kim ,  Hongsoo Jeon

    IPC: G11C16/08 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

    Abstract: A nonvolatile memory device includes first and second semiconductor layers and pass transistors. The first semiconductor layer includes wordlines that extend in a first direction and bitlines that extend in a second direction, and further includes a first substrate and a memory cell array. The memory cell array is on the first substrate and connected to the wordlines and the bitlines. The second semiconductor layer is arranged with respect to the first semiconductor layer in a third direction, and includes a second substrate and a peripheral circuit. The peripheral circuit is on the second substrate and controls the memory cell array. The pass transistors are connected to the wordlines and control an electrical connection between the memory cell array and the peripheral circuit. A first part of the pass transistors are in the first semiconductor layer, and a second part of the pass transistors are in the second semiconductor layer.

    INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20210202496A1

    公开(公告)日：2021-07-01

    申请号：US16935607

    申请日：2020-07-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANGWAN NAM ,  Yongseok Kwon ,  Hongsoo Jeon

    IPC: H01L27/115 ,  H01L23/48 ,  H01L23/522

    Abstract: An integrated circuit device includes; a peripheral circuit structure, a cell array structure including gate lines overlapping the peripheral circuit structure and disposed on the peripheral circuit structure in a vertical direction, a conductive plate interposed between the peripheral circuit structure and the cell array structure and including through holes, conductive lines spaced apart from the conductive plate with the cell array structure interposed between the conductive lines and the conductive plate, and through electrodes connected to the conductive lines and extending to the peripheral circuit structure through the cell array structure and the through holes. The through holes include a first through holes arranged along a first straight line extending in a first horizontal direction, and second through holes arranged along a second straight line extending in parallel with the first straight line and spaced apart from the first straight line in a second horizontal direction.

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