Invention Publication
- Patent Title: CAPACITOR SEPARATIONS IN DIELECTRIC LAYERS
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Application No.: US18109780Application Date: 2023-02-14
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Publication No.: US20230200043A1Publication Date: 2023-06-22
- Inventor: Travis W. LAJOIE , Abhishek A. SHARMA , Van H. LE , Chieh-Jen KU , Pei-Hua WANG , Jack T. KAVALIEROS , Bernhard SELL , Tahir GHANI , Gregory GEORGE , Akash GARG , Julie ROLLINS , Allen B. GARDINER , Shem OGADHOH , Juan G. ALZATE VINASCO , Umut ARSLAN , Fatih HAMZAOGLU , Nikhil MEHTA , Yu-Wen HUANG , Shu ZHOU
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- The original application number of the division: US16457657 2019.06.28
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
Public/Granted literature
- US11991873B2 Capacitor separations in dielectric layers Public/Granted day:2024-05-21
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