公开(公告)号：US20220320275A1

公开(公告)日：2022-10-06

申请号：US17848224

申请日：2022-06-23

申请人： Intel Corporation

发明人： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen B. GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L27/105 ,  H01L21/02 ,  H01L29/423 ,  H01L21/764 ,  H01L21/768

摘要： An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US20200303520A1

公开(公告)日：2020-09-24

申请号：US16361881

申请日：2019-03-22

申请人： Intel Corporation

发明人： Chieh-Jen KU ,  Bernhard SELL ,  Pei-Hua WANG ,  Nikhil MEHTA ,  Shu ZHOU ,  Jared STOEGER ,  Allen B. GARDINER ,  Akash GARG ,  Shem OGADHOH ,  Vinaykumar HADAGALI ,  Travis W. LAJOIE

IPC分类号： H01L29/66 ,  H01L27/108 ,  H01L29/786

摘要： An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

公开(公告)号：US20240049450A1

公开(公告)日：2024-02-08

申请号：US18381119

申请日：2023-10-17

申请人： Intel Corporation

发明人： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Jared STOEGER ,  Yu-Wen HUANG ,  Shu ZHOU

IPC分类号： H10B12/00 ,  H01L27/12

CPC分类号： H10B12/315 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1225 ,  H01L28/82 ,  H01L27/1248 ,  H01L27/1255 ,  H01L28/55 ,  H01L28/65 ,  H01L27/124 ,  H10B12/312 ,  H10B12/0335

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20210366821A1

公开(公告)日：2021-11-25

申请号：US17398933

申请日：2021-08-10

申请人： Intel Corporation

发明人： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

摘要： An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20230200043A1

公开(公告)日：2023-06-22

申请号：US18109780

申请日：2023-02-14

申请人： Intel Corporation

发明人： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Julie ROLLINS ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Yu-Wen HUANG ,  Shu ZHOU

IPC分类号： H10B12/00

CPC分类号： H10B12/03 ,  H10B12/05 ,  H10B12/30

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20190304897A1

公开(公告)日：2019-10-03

申请号：US15943565

申请日：2018-04-02

申请人： Intel Corporation

发明人： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L27/108

摘要： An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.