- 专利标题： INTEGRATED CIRCUIT WITH NANOSHEET TRANSISTORS WITH METAL GATE PASSIVATION
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申请号： US17381006申请日： 2021-07-20
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公开(公告)号： US20230029370A1公开(公告)日： 2023-01-26
- 发明人: Mao-Lin HUANG , Lung-Kun CHU , Chung-Wei HSU , Jia-Ni YU , Kuo-Cheng CHIANG , Kuan-Lun CHENG , Chih-Hao WANG
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 主分类号： H01L21/28
- IPC分类号： H01L21/28 ; H01L27/092 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L21/02 ; H01L21/8238 ; H01L29/66
摘要：
A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a metal gate layer for the P-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistor.
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