Invention Publication
- Patent Title: DYNAMIC CACHE BYPASS FOR POWER SAVINGS
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Application No.: US17730041Application Date: 2022-04-26
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Publication No.: US20230341922A1Publication Date: 2023-10-26
- Inventor: Ashish Jain , Benjamin Tsien , Chintan S. Patel , Vydhyanathan Kalyanasundharam , Shang Yang
- Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee Address: US CA Santa Clara; CA Markham
- Main IPC: G06F1/3287
- IPC: G06F1/3287 ; G06F1/3234 ; G06F12/0891
Abstract:
A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.
Public/Granted literature
- US11899520B2 Dynamic cache bypass for power savings Public/Granted day:2024-02-13
Information query
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