公开(公告)号：US20230341922A1

公开(公告)日：2023-10-26

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

公开(公告)号：US20240103754A1

公开(公告)日：2024-03-28

申请号：US17936345

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Gia Tung Phan ,  Ashish Jain ,  Chintan S. Patel ,  Benjamin Tsien ,  Jun Lei ,  Shang Yang ,  Oswin Hall

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679

Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.

公开(公告)号：US11899520B2

公开(公告)日：2024-02-13

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

公开(公告)号：US12093181B2

公开(公告)日：2024-09-17

申请号：US17852296

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alexander J. Branover ,  Benjamin Tsien ,  Edgar Munoz ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0864 ,  G06F12/0871

CPC classification number: G06F12/0871 ,  G06F12/0811 ,  G06F12/0864

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.

公开(公告)号：US20240220409A1

公开(公告)日：2024-07-04

申请号：US18090249

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Vydhyanathan Kalyanasundharam ,  Alan D. Smith ,  Chintan S. Patel ,  William L. Walker

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/1024

Abstract: The disclosed computer-implemented method includes partitioning a cache structure into a plurality of cache partitions designated by a plurality of cache types, forwarding a memory request to a cache partition corresponding to a target cache type of the memory request, and performing, using the cache partition, the memory request. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11874774B2

公开(公告)日：2024-01-16

申请号：US17031834

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Ganesh Balakrishnan ,  Joe Sargunaraj ,  Chintan S. Patel ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/08 ,  G06F12/0891 ,  G06F9/46 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F9/467 ,  G06F12/084 ,  G06F12/0813 ,  G06F12/0833

Abstract: A method includes, in response to each write request of a plurality of write requests received at a memory-side cache device coupled with a memory device, writing payload data specified by the write request to the memory-side cache device, and when a first bandwidth availability condition is satisfied, performing a cache write-through by writing the payload data to the memory device, and recording an indication that the payload data written to the memory-side cache device matches the payload data written to the memory device.

公开(公告)号：US11755477B2

公开(公告)日：2023-09-12

申请号：US17563675

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Girish Balaiah Aswathaiya

IPC: G06F12/00 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/604

Abstract: A cache includes an upstream port, a downstream port, a cache memory, and a control circuit. The control circuit temporarily stores memory access requests received from the upstream port, and checks for dependencies for a new memory access request with older memory access requests temporarily stored therein. If one of the older memory access requests creates a false dependency with the new memory access request, the control circuit drops an allocation of a cache line to the cache memory for the older memory access request while continuing to process the new memory access request.

公开(公告)号：US20230195644A1

公开(公告)日：2023-06-22

申请号：US17556617

申请日：2021-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Chintan S. Patel ,  Guhan Krishnan ,  Andrew William Lueck ,  Sreenath Thangarajan

IPC: G06F12/0897

CPC classification number: G06F12/0897 ,  G06F2212/60

Abstract: A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

公开(公告)号：US20190319891A1

公开(公告)日：2019-10-17

申请号：US15951844

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan Dodson Smith ,  Vydhyanathan Kalyanasundharam ,  Bryan P. Broussard ,  Greggory D. Donley ,  Chintan S. Patel

IPC: H04L12/873 ,  H04L12/877 ,  H04L12/841 ,  H04L12/875

Abstract: A computing system uses a memory for storing data, one or more clients for generating network traffic and a communication fabric with network switches. The network switches include centralized storage structures, rather than separate input and output storage structures. The network switches store particular metadata corresponding to received packets in a single, centralized collapsing queue where the age of the packets corresponds to a queue entry position. The payload data of the packets are stored in a separate memory, so the relatively large amount of data is not shifted during the lifetime of the packet in the network switch. The network switches select sparse queue entries in the collapsible queue, deallocate the selected queue entries, and shift remaining allocated queue entries toward a first end of the queue with a delay proportional to the radix of the network switches.

公开(公告)号：US20230418753A1

公开(公告)日：2023-12-28

申请号：US17852296

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Chintan S. Patel ,  Alexander J. Branover ,  Benjamin Tsien ,  Edgar Munoz ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0871 ,  G06F12/0864 ,  G06F12/0811

CPC classification number: G06F12/0871 ,  G06F12/0811 ,  G06F12/0864

Abstract: A technique for operating a cache is disclosed. The technique includes based on a workload change, identifying a first allocation permissions policy; operating the cache according to the first allocation permissions policy; based on set sampling, identifying a second allocation permissions policy; and operating the cache according to the second allocation permissions policy.