Invention Publication
- Patent Title: 3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND NMOS
-
Application No.: US17833050Application Date: 2022-06-06
-
Publication No.: US20230395718A1Publication Date: 2023-12-07
- Inventor: Willy Rachmady , Nitesh Kumar , Jami A. Wiedemer , Cheng-Ying Huang , Marko Radosavljevic , Mauro J. Kobrinsky , Patrick Morrow , Rohit Galatage , David N. Goldstein , Christopher J. Jezewski
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/423 ; H01L29/45 ; H01L29/06 ; H01L27/092

Abstract:
An integrated circuit structure includes a vertical stack including a first device, and a second device above the first device. The first device includes (i) a first source and first drain region, (ii) a first body laterally between the first source and drain regions, (iii) a first source contact including a first conductive material, and (iv) a first drain contact including the first conductive material. The second device includes (i) a second source and second drain region, (ii) a second body laterally between the second source and drain regions, (iii) a second source contact including a second conductive material, and (iv) a second drain contact including the second conductive material. In an example, the first and second conductive materials are compositionally different. In an example, the first conductive material induces compressive strain on the first body, and the second conductive material induces tensile strain on the second body.
Information query
IPC分类: