发明公开
- 专利标题: PACKAGE ARCHITECTURE WITH VERTICALLY STACKED BRIDGE DIES HAVING PLANARIZED EDGES
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申请号: US17846129申请日: 2022-06-22
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公开(公告)号: US20230420410A1公开(公告)日: 2023-12-28
- 发明人: Sagar Suthram , Ravindranath Vithal Mahajan , Debendra Mallik , Omkar G. Karhade , Wilfred Gomes , Pushkar Sharad Ranade , Abhishek A. Sharma , Tahir Ghani , Anand S. Murthy , Nitin A. Deshpande
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L25/065
- IPC分类号: H01L25/065 ; H01L23/00 ; H01L23/522 ; H01L23/46 ; H01L25/00
摘要:
Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.
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