公开(公告)号：US20240222326A1

公开(公告)日：2024-07-04

申请号：US18148528

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H10B10/00 ,  H10B12/00 ,  H10B80/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5283 ,  H10B10/12 ,  H10B12/37 ,  H10B80/00

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit; a second IC die; a third IC die; and a package substrate. The first IC die is between the second IC die and the package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240004129A1

公开(公告)日：2024-01-04

申请号：US17853732

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  John Heck ,  Pushkar Sharad Ranade ,  Ravindranath Vithal Mahajan ,  Thomas Liljeberg ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani

IPC: G02B6/12 ,  G02B6/13 ,  H01L25/16 ,  H01L23/00

CPC classification number: G02B6/12002 ,  G02B6/12004 ,  G02B6/13 ,  H01L25/167 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in an array; and a plurality of photonic integrated circuit (PIC) dies, each PIC die having waveguides. Adjacent microelectronic sub-assemblies are coupled to one of the PIC dies by interconnects such that any one PIC die is coupled to more than two adjacent microelectronic sub-assemblies, and the microelectronic sub-assemblies coupled to each PIC die in the plurality of PIC dies are communicatively coupled by the waveguides in the PIC die. Each microelectronic sub-assembly comprises: an interposer integrated circuit (IC) die comprising one or more electrical controller circuit proximate to at least one edge of the interposer IC die; a first plurality of IC dies coupled to a first surface of the interposer IC die; and a second plurality of IC dies coupled to an opposing second surface of the interposer IC die.

公开(公告)号：US20230395676A1

公开(公告)日：2023-12-07

申请号：US17829706

申请日：2022-06-01

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand S. Murthy ,  Pushkar Sharad Ranade

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L29/4238 ,  H01L29/0665 ,  H01L29/42392 ,  H01L27/092

Abstract: IC devices with transistors having angled gates, and related assemblies and methods, are disclosed herein. A transistor is referred to as having an “angled gate” if an angle between a projection of the gate of the transistor onto a plane of a support structure (e.g., a die) over which the transistor is implemented and an analogous projection of a longitudinal axis of an elongated structure (e.g., a fin or a nanoribbon having one or more semiconductor materials) based on which the transistor is built is between 10 degrees and 80 degrees. Transistors having angled gates provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips and/or decreasing short-channel effects associated with continuous scaling of IC components.

公开(公告)号：US20240105596A1

公开(公告)日：2024-03-28

申请号：US17935627

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Shem Ogadhoh ,  Pushkar Sharad Ranade ,  Sagar Suthram ,  Elliot Tan

IPC: H01L23/528 ,  H01L23/498

CPC classification number: H01L23/528 ,  H01L23/49838 ,  H01L24/16

Abstract: IC devices with angled interconnects are disclosed herein. An interconnect, specifically a trench or line interconnect, is referred to as an “angled interconnect” if the interconnect is neither perpendicular nor parallel to any edges of front or back faces of the support structure, or if the interconnect is not parallel or perpendicular to interconnect in another region of an interconnect layer. Angled interconnects may be used to decrease the area of pitch transition regions. Angled interconnects may also be used to decrease the area of pitch offset regions.

公开(公告)号：US20240008255A1

公开(公告)日：2024-01-04

申请号：US18325492

申请日：2023-05-30

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Sagar Suthram ,  Tahir Ghani ,  Anand S. Murthy ,  Cory E. Weber ,  Rishabh Mehandru ,  Wilfred Gomes ,  Pushkar Sharad Ranade

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/05 ,  H10B12/482

Abstract: Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

公开(公告)号：US20240006395A1

公开(公告)日：2024-01-04

申请号：US17853778

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma

IPC: H01L25/16 ,  H01L23/492 ,  H01L23/522 ,  H01L23/528 ,  H01L23/04 ,  H01L23/46 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/167 ,  H01L23/492 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/04 ,  H01L2224/80895 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L24/96 ,  H01L2224/08146 ,  H01L23/46

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

公开(公告)号：US20230420410A1

公开(公告)日：2023-12-28

申请号：US17846129

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/46 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L23/46 ,  H01L24/94 ,  H01L24/96 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/08137 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first IC die coupled to at least two second IC dies by interconnects on a first surface of the first IC die and second surfaces of the second IC dies such that the first surface is in contact with the second surfaces. The second surfaces are coplanar, the interconnects comprise dielectric-dielectric bonds and metal-metal bonds, the metal-metal bonds include first bond-pads in the first IC die and second bond-pads in the second IC dies, the first IC die comprises a substrate attached to a metallization stack along a planar interface that is orthogonal to the first surface, the metallization stack comprises a plurality of layers of conductive traces in a dielectric material, and the first bond-pads comprise portions of the conductive traces exposed on the first surface.

公开(公告)号：US20230275151A1

公开(公告)日：2023-08-31

申请号：US17680365

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Anand S. Murthy ,  Tahir Ghani ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L21/823807

Abstract: Hybrid FETs and methods of forming such hybrid FETs are disclosed. An example hybrid FET includes a channel region, a first region, a second region, a third region, and two gates. A gate may wrap around a portion of the channel region. The channel region may be over a first substrate (e.g., a substrate on which the channel region is formed) but cross a second substrate. The channel region is shared by a MOSFET and a TFET. The first region and second region constitute the source and drain of the MOSFET and are doped with dopants of the same type. The first region and third region constitute the source and drain of the TFET and are doped with dopants of opposite types. The third region may be placed at the opposite side of the second substrate from the first region and the second region.

公开(公告)号：US20240222328A1

公开(公告)日：2024-07-04

申请号：US18148543

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Wilfred Gomes ,  Nisha Ananthakrishnan ,  Kemal Aygun ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/39

Abstract: Embodiments of a microelectronic assembly include: a first integrated circuit (IC) die having a first memory circuit and a second memory circuit, a second IC die; a third IC die; and a package substrate. The first IC die comprises: a first portion comprising a first active region and a first backend region in contact with the first active region; and a second portion comprising a second active region and a second backend region in contact with the second active region. The second portion is surrounded by the first portion in plan view, the first memory circuit is in the first portion, the second memory circuit is in the second portion, the first active region comprises transistors that are larger than transistors in the second active region, and the first backend region comprises conductive traces that have a larger pitch than conductive traces in the second backend region.

公开(公告)号：US20240088017A1

公开(公告)日：2024-03-14

申请号：US17930825

申请日：2022-09-09

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40

Abstract: Described herein are full wafer devices that include passive devices formed in one or more interconnect layers. Interconnect layers are formed over a front side of the full wafer device. A passive device is formed using an additive process that results in a seam running through the passive device. The seam may be, for example, an air gap, a change in material structure, or a region with a different chemical makeup from the surrounding passive device. In some embodiments, the passive devices are formed in global interconnect layers coupling multiple does of the full wafer device.