A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.