公开(公告)号：US11842774B2

公开(公告)日：2023-12-12

申请号：US17583537

申请日：2022-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gianfranco Valeri ,  Violante Moschiano ,  Walter Di-Francesco

IPC: G11C13/00 ,  G11C16/28 ,  G06F11/10 ,  G11C16/10

CPC classification number: G11C16/28 ,  G06F11/1008 ,  G11C13/004 ,  G11C16/107

Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.

公开(公告)号：US10423350B2

公开(公告)日：2019-09-24

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10818363B1

公开(公告)日：2020-10-27

申请号：US16414897

申请日：2019-05-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gianfranco Valeri ,  Violante Moschiano ,  Walter Di-Francesco

IPC: G11C13/00 ,  G11C16/28 ,  G06F11/10 ,  G11C16/10

Abstract: Methods of operating a memory, and apparatus configured to perform similar methods, include determining first states of a first sense node and a second sense node while a first voltage level is capacitively coupled to the first sense node and while a second voltage level is capacitively coupled to the second sense node, determining a second states of the first and second sense nodes while a third voltage level is capacitively coupled to the first sense node and while a fourth voltage level is capacitively coupled to the second sense node, determining a fifth voltage level in response to at least the first states of the first and second sense nodes and the second states of the first and second sense nodes, and determining third states of the first and second sense nodes while the fifth voltage level is capacitively coupled to the first and second sense nodes.

公开(公告)号：US20180210653A1

公开(公告)日：2018-07-26

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US20230134281A1

公开(公告)日：2023-05-04

申请号：US17976423

申请日：2022-10-28

Applicant: Micron Technology, Inc.

Inventor： Leo Raimondo ,  Federica Paolini ,  Umberto Siciliani ,  Violante Moschiano ,  Gianfranco Valeri ,  Davide Esposito ,  Walter Di Francesco

IPC: G11C16/34 ,  G11C16/10

Abstract: A memory device includes an array of memory cells configured as single-level cell memory and control logic operatively coupled to the array of memory cells. The control logic performs operations including: causing hardware initialization of a set of sub-blocks that are to be programmed within the array of memory cells; causing a first sub-block of the set of sub-blocks to be preconditioned for a program operation; causing multiple pages of data to be programmed to respective ones of the set of sub-blocks; and selectively causing a program verify to be performed on memory cells of the set of sub-blocks after programming the multiple pages of data.

公开(公告)号：US20210103389A1

公开(公告)日：2021-04-08

申请号：US17123472

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US11416154B2

公开(公告)日：2022-08-16

申请号：US17123472

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US20190286328A1

公开(公告)日：2019-09-19

申请号：US16428011

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10359963B2

公开(公告)日：2019-07-23

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US20220148661A1

公开(公告)日：2022-05-12

申请号：US17583537

申请日：2022-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gianfranco Valeri ,  Violante Moschiano ,  Walter Di-Francesco

IPC: G11C16/26 ,  G11C16/04

Abstract: Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.