Invention Publication
- Patent Title: SELECTIVE DEPOSITION OF LINER AND BARRIER FILMS FOR RESISTANCE REDUCTION OF SEMICONDUCTOR DEVICES
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Application No.: US17882821Application Date: 2022-08-08
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Publication No.: US20240047342A1Publication Date: 2024-02-08
- Inventor: Jeffrey SMITH , Hiroaki NIIMI , Kandabara TAPILY , Daniel CHANEMOUGAME , Lars LIEBMANN
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L29/08 ; H01L21/768 ; H01L21/762

Abstract:
A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/ID structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier.
Information query
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