公开(公告)号：US20220367461A1

公开(公告)日：2022-11-17

申请号：US17737640

申请日：2022-05-05

Applicant: Tokyo Electron Limited

Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Paul GUTWIN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the semiconductor structure can include a lower semiconductor device tier including lower semiconductor devices, an upper semiconductor device tier disposed over the lower semiconductor device tier and including upper semiconductor devices, a separation layer disposed between and separating the lower and upper semiconductor device tiers, a wiring tier disposed below the lower semiconductor device tier, a lower gate contact extending from a lower gate region of the lower semiconductor device tier downward to the wiring tier, an upper gate contact extending from an upper gate region of the upper semiconductor device tier downward through the separation layer to the wiring tier, and an isolator covering a lateral surface of the upper gate contact and electrically isolating the upper and lower gate contacts. The lower gate contact and the upper gate contact can be independent from each other.

公开(公告)号：US20220102380A1

公开(公告)日：2022-03-31

申请号：US17326449

申请日：2021-05-21

Applicant: Tokyo Electron Limited

Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH

IPC: H01L27/12 ,  H01L23/528 ,  H01L21/84 ,  H01L21/74 ,  H01L23/535

Abstract: In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.

公开(公告)号：US20210098294A1

公开(公告)日：2021-04-01

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Hiroki NIIMI ,  Kandabara TAPILY ,  Subhadeep KAL ,  Jodi GRZESKOWIAK ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.

公开(公告)号：US20210043522A1

公开(公告)日：2021-02-11

申请号：US16848638

申请日：2020-04-14

Applicant: TOKYO ELECTRON LIMITED

Inventor： Daniel CHANEMOUGAME ,  Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method of manufacturing a 3D semiconductor device, the method including forming a first target structure, the first target structure including at least one upper gate, at least one bottom gate, and a dielectric separation layer disposed between and separating the at least one upper gate and the at least one bottom gate; removing material in a plurality of material removal areas in the first target structure, the plurality of material removal areas including at least one material removal area that extends through the at least one upper gate to a top of the dielectric separation layer; and forming a first contact establishing a first electrical connection to the upper gate and a second contact establishing a second electrical connection to the at least one bottom gate, such that the first contact and second contact are independent of each other

公开(公告)号：US20230326855A1

公开(公告)日：2023-10-12

申请号：US18331651

申请日：2023-06-08

Applicant: Tokyo Electron Limited

Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Anton J. DEVILLIERS

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L21/76895 ,  H01L21/76877 ,  H01L23/5226

Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor device. For example, the method can include forming a first power rail, forming a first power input structure for coupling with a first terminal of a power source that is external of the semiconductor device to receive electrical power from the power source, forming an active device between the first power rail and the first power input structure, and forming a first middle-of-line rail with a plurality of layers. The first middle-of-line rail can be configured to deliver the electrical power from the first power input structure to the first power rail. The first power rail can provide the electrical power to the active device for operation. Topmost and bottommost ones of the layers of the first middle-of-line rail can be as high as and leveled with top and bottom surfaces of the active device, respectively.

公开(公告)号：US20230100332A1

公开(公告)日：2023-03-30

申请号：US18074684

申请日：2022-12-05

Applicant: Tokyo Electron Limited

Inventor： Lars LIEBMANN ,  Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Paul GUTWIN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

公开(公告)号：US20230017350A1

公开(公告)日：2023-01-19

申请号：US17836019

申请日：2022-06-09

Applicant: Tokyo Electron Limited

Inventor： Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Jeffrey SMITH ,  Paul GUTWIN

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/768 ,  H01L21/822 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a method of manufacturing a three-dimensional (3D) semiconductor device. For example, the method can include forming a target structure, the target structure including a lower gate region, an upper gate region, and a separation layer disposed between and separating the lower gate region and the upper gate region. The method can also include forming a sacrificial contact structure extending vertically from the bottom gate region through the separation layer and the upper gate region to a position above the upper gate region, removing at least a portion of the sacrificial contact structure resulting in a lower gate contact opening extending from the position above the upper gate region to the bottom gate region, insulating a side wall surface of the lower gate contact opening, and filling the lower gate contact opening with a conductor to form a lower gate contact.

公开(公告)号：US20210202500A1

公开(公告)日：2021-07-01

申请号：US17139303

申请日：2020-12-31

Applicant: Tokyo Electron Limited

Inventor： Daniel CHANEMOUGAME ,  Lars Liebmann ,  Jeffrey Smith

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A static random access memory (SRAM) structure is provided. The structure includes a plurality of SRAM bit cells on a substrate. Each SRAM bit cell includes at least six transistors including at least two NMOS transistors and at least two PMOS transistors. Each of the six transistors is being lateral gate-all-around transistors in that gates wraps all around a cross section of channels of the at least six transistors. The at least six transistors positioned in three decks in which a third deck is positioned vertically above a second deck, and the second deck is positioned vertically above a first deck relative to a working surface of the substrate. A first inverter is formed using a first transistor positioned in the first deck and a second transistor positioned in the second deck. A second inverter is formed using a third transistor positioned in the first deck and a fourth transistor positioned in the second deck. A pass gate is located in the third deck.

公开(公告)号：US20240047342A1

公开(公告)日：2024-02-08

申请号：US17882821

申请日：2022-08-08

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Hiroaki NIIMI ,  Kandabara TAPILY ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN

IPC: H01L23/522 ,  H01L29/08 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L23/5226 ,  H01L29/0847 ,  H01L21/76879 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76224

Abstract: A semiconductor device includes a field-effect transistor (FET) having a source/drain (S/D) structure and an interconnect structure in contact with the S/D structure. The interconnect structure has a barrier film at a surface of the interconnect structure separating the interconnect structure from materials surrounding the interconnect structure. A first portion of the barrier film covers a first interface between the interconnect structure and the S/ID structure. A second portion of the barrier film covers a second interface between the interconnect structure and dielectric materials adjacent to the interconnect structure. The first portion of the barrier film is thicker than the second portion of the barrier.

公开(公告)号：US20230036597A1

公开(公告)日：2023-02-02

申请号：US17878457

申请日：2022-08-01

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Daniel CHANEMOUGAME ,  Lars LIEBMANN ,  Paul GUTWIN ,  Subhadeep KAL ,  Kandabara TAPILY ,  Anton DEVILLIERS

IPC: H01L21/822 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a self-aligned microfabrication method, which can include providing a substrate having vertically arranged first and second channel structures, forming first and second sacrificial contacts to cover ends of the first and second channel structures, respectively, covering the first and second sacrificial contacts with a fill material, recessing the fill material such that the second sacrificial contact is at least partially uncovered while the first sacrificial contact remains covered, replacing the second sacrificial contact with a cover spacer, removing a remaining portion of the first fill material, uncovering the end of the first channel structure, forming a first source/drain (S/D) contact to cover the end of the first channel structure, covering the first S/D contact with a second fill material, uncovering the end of the second channel structure, and forming a second S/D contact at the end of the second channel structure.