公开(公告)号：US20220416048A1

公开(公告)日：2022-12-29

申请号：US17851975

申请日：2022-06-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Paul GUTWIN ,  Kandabara TAPILY ,  Subhadeep KAL ,  Robert CLARK

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

Abstract: Aspects of the present disclosure provide a method, which includes providing a semiconductor structure including a first lower semiconductor device and a first upper semiconductor device stacked vertically over the first lower semiconductor device. The first lower semiconductor device has one or more first lower channels. The first upper semiconductor device has one or more first upper channels. First work function metal (WFM) can cover the first lower channels and the first upper channels. The method can also include recessing the first WFM to uncover the first upper channels of the first upper semiconductor device, depositing a monolayer on uncovered dielectric surfaces of the semiconductor structure, depositing isolation dielectric on the first WFM of the first lower semiconductor device, and depositing second WFM to cover the first upper channels of the first upper semiconductor device. The isolation dielectric isolates the first lower semiconductor device from the first upper semiconductor device.

公开(公告)号：US20180047832A1

公开(公告)日：2018-02-15

申请号：US15674012

申请日：2017-08-10

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kandabara TAPILY ,  Jeffrey SMITH ,  Nihar MOHANTY ,  Anton J. DEVILLIERS

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

Abstract: A method of forming a semiconductor device having a channel and a source-drain coupled to the channel. The method includes etching a channel region such that an end of the channel region forms a recess within a gate structure surrounding the channel region. An extension region is formed in contact with the channel region and at least partially filling the recess. Extension material of the extension region has a different composition from channel material of the channel region such that a strain is caused in the channel region. A source-drain region is in contact with the extension region and adjacent to the gate structure.

公开(公告)号：US20220181176A1

公开(公告)日：2022-06-09

申请号：US17682202

申请日：2022-02-28

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kandabara TAPILY

IPC: H01L21/67 ,  H01L21/66 ,  H01L21/311 ,  H01L21/02 ,  C23C16/06 ,  C23C16/40 ,  C23C16/02 ,  C23C16/56

Abstract: A substrate processing method includes (a) providing a substrate in a substrate processing tool, the substrate containing an exposed surface of a first material layer and an exposed surface of a second material layer; (b) forming a self-assembled monolayer (SAM) on the substrate in a first substrate processing chamber (SPC); (c) transferring the substrate from the first SPC through a substrate transfer chamber to a second SPC; (d) depositing a film selectively on the first material layer and film nuclei on the SAM in the second SPC; (e) transferring, after selectively depositing the film on the first material layer, the substrate from the second SPC through the substrate transfer chamber to a third SPC; (f) removing the film nuclei from the SAM by etching in the third SPC; and repeating (b), (c), (d), (e) and (f) sequentially at least once.

公开(公告)号：US20210013111A1

公开(公告)日：2021-01-14

申请号：US16924937

申请日：2020-07-09

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Kandabara TAPILY ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Mark GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423

Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.

公开(公告)号：US20250079166A1

公开(公告)日：2025-03-06

申请号：US18786164

申请日：2024-07-26

Applicant: Tokyo Electron Limited

Inventor： Panupong JAIPAN ,  Matthew BARON ,  Kandabara TAPILY ,  Ilseok SON ,  Arkalgud SITARAM ,  Yohei YAMASHITA ,  Yasutaka MIZOMOTO ,  Yoshihiro TSUTSUMI ,  Yoshihiro KONDO

IPC: H01L21/02 ,  H01L21/306

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first device structure on a first substrate, a first laser liftoff layer on the first device structure, a protective layer on the first laser liftoff layer, and a second substrate on the protective layer. The method includes de-attaching, through applying radiation on the first laser liftoff layer, the protective layer from the first laser liftoff layer, with a first surface of the second substrate remaining in contact with a second surface of the protective layer. The protective layer is transparent to the radiation.

公开(公告)号：US20210249305A1

公开(公告)日：2021-08-12

申请号：US17223831

申请日：2021-04-06

Applicant: Tokyo Electron Limited

Inventor： Kandabara TAPILY ,  Jeffrey SMITH

IPC: H01L21/768 ,  H01L23/522

Abstract: A semiconductor device includes conductive structures formed in a first dielectric layer, a conductive cap layer selectively positioned over the conductive structures and the first dielectric layer with a top surface and sidewalls, a second dielectric layer selectively positioned over the first dielectric layer and disposed between the sidewalls of the conductive cap layer, a third dielectric layer selectively positioned over the second dielectric layer and disposed between the sidewalls of the conductive cap layer, a fourth dielectric layer arranged over the conductive structures and the third dielectric layer, and an interconnect structure formed in the fourth dielectric layer. The interconnect structure includes a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure. The via structure includes a first portion positioned over the conductive cap layer and a second portion disposed over the first portion and the third dielectric layer.

公开(公告)号：US20180374791A1

公开(公告)日：2018-12-27

申请号：US16011377

申请日：2018-06-18

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Anton J. DEVILLIERS ,  Kandabara TAPILY

IPC: H01L23/528 ,  H01L29/06 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768

Abstract: Aspects of the disclosure provide a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric cap that isolates the power rail from conductive pattern structures on the dielectric cap. Further, an opening is selectively formed in the dielectric cap and is filled with conductive material to selectively connect a conductive pattern structure with the power rail.

公开(公告)号：US20250129475A1

公开(公告)日：2025-04-24

申请号：US18493419

申请日：2023-10-24

Applicant: Tokyo Electron Limited

Inventor： Norman JACOBSON ,  Ronald NASMAN ,  Kandabara TAPILY

IPC: C23C16/455 ,  C23C16/458

Abstract: Aspects of the present disclosure provide an apparatus, which includes first gas channels distributing a first process gas and second gas channels alternating with the first gas channels and distributing a second process gas. The apparatus further includes first feed tubes each including first outlets configured to deliver the first process gas to a row of the first gas channels via the first outlets along different first flow paths of a same first length, and second feed tubes each including second outlets corresponding to a row of the second gas channels and configured to deliver the second process gas to the row of the second gas channels via the second outlets along different second flow paths of a same second length. The apparatus further includes vertical gas conduits each vertically extending from a respective one of the array of gas channels configured to transmit the first or second process gas.

公开(公告)号：US20210125863A1

公开(公告)日：2021-04-29

申请号：US17140310

申请日：2021-01-04

Applicant: Tokyo Electron Limited

Inventor： Robert CLARK ,  Kandabara TAPILY ,  Kai-Hung YU

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

公开(公告)号：US20210098294A1

公开(公告)日：2021-04-01

申请号：US17034930

申请日：2020-09-28

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  Lars LIEBMANN ,  Daniel CHANEMOUGAME ,  Hiroki NIIMI ,  Kandabara TAPILY ,  Subhadeep KAL ,  Jodi GRZESKOWIAK ,  Anton DEVILLIERS

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/8234 ,  H01L29/66

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming BPR structures filled with a replacement BPR material, first S/D structures, first replacement silicide layers, and a pre-metallization dielectric that covers the first replacement silicide layers and the first S/D structures. The method also includes forming first interconnect openings in the pre-metallization dielectric and first replacement interconnect layers in the first interconnect openings. The first replacement interconnect layers are connected to the first replacement silicide layers. A thermal process is executed. The method further includes replacing, from a first side of the first wafer, a first group of the first replacement interconnect layers, a first group of the first replacement silicide layers, and the replacement BPR material, and replacing, from a second side of the first wafer, a second group of the first replacement interconnect layers, and a second group of the first replacement silicide layers.