Invention Publication
- Patent Title: SOURCE AND DRAIN REGIONS FOR LATERALLY ADJACENT GATE-ALL-AROUND (GAA) PMOS AND NMOS
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Application No.: US17896813Application Date: 2022-08-26
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Publication No.: US20240071831A1Publication Date: 2024-02-29
- Inventor: Chang Wan Han , Biswajeet Guha , Vivek Thirtha , William Hsu , Ian Yang , Oleg Golonzka , Kevin J. Fischer , Suman Dasgupta , Sameerah Desnavi , Deepak Sridhar
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/06 ; H01L29/08 ; H01L29/417 ; H01L29/423 ; H01L29/66 ; H01L29/775 ; H01L29/778 ; H01L29/786
Abstract:
An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure
Information query
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