公开(公告)号：US20240071831A1

公开(公告)日：2024-02-29

申请号：US17896813

申请日：2022-08-26

Applicant: INTEL CORPORATION

Inventor： Chang Wan Han ,  Biswajeet Guha ,  Vivek Thirtha ,  William Hsu ,  Ian Yang ,  Oleg Golonzka ,  Kevin J. Fischer ,  Suman Dasgupta ,  Sameerah Desnavi ,  Deepak Sridhar

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An integrated circuit includes laterally adjacent first and second devices. The first device includes a first source or drain region, a first gate structure, and a first inner spacer between the first source or drain region and the first gate structure. The second device includes a second source or drain region, a second gate structure, and a second inner spacer between the second source or drain region and the second gate structure. In an example, the first source or drain region has a width that is at least 1 nanometer different from a width of the second source or drain region, and/or the first inner spacer has a width that is at least 1 nanometer different from a width of the second inner spacer. The various widths are measured in a direction of a semiconductor body between the first source or drain region and the first gate structure