公开(公告)号：US11837641B2

公开(公告)日：2023-12-05

申请号：US16719281

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L29/41 ,  H01L29/417 ,  H01L25/18 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L25/18 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/7853 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US11756829B2

公开(公告)日：2023-09-12

申请号：US17961400

申请日：2022-10-06

Applicant: Intel Corporation

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/768 ,  H01L21/306 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/66 ,  H01L21/28 ,  H01L23/535 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545 ,  H01L21/32

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US11721630B2

公开(公告)日：2023-08-08

申请号：US17723309

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20230197818A1

公开(公告)日：2023-06-22

申请号：US17559342

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Nitesh Kumar ,  William Hsu ,  Mohammad Hasan ,  Ritesh Das ,  Vivek Thirtha ,  Biswajeet Guha ,  Oleg Golonzka

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823412 ,  H01L21/823418

Abstract: Methods, integrated circuit devices, and systems are discussed related to combining source and drain etch, cavity spacer formation, and source and drain semiconductor growth into a single lithographic processing step in gate-all-around transistors. Such combined processes are performed separately for NMOS and PMOS gate-all-around transistors by implementing selective masking techniques. The resulting transistor structures have improved cavity spacer integrity and contact to gate isolation.

公开(公告)号：US11569370B2

公开(公告)日：2023-01-31

申请号：US16454408

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Vivek Thirtha ,  Shu Zhou ,  Nitesh Kumar ,  Biswajeet Guha ,  William Hsu ,  Dax Crum ,  Oleg Golonzka ,  Tahir Ghani ,  Christopher Kenyon

IPC: H01L29/66 ,  H01L21/31 ,  H01L29/06 ,  H01L21/3105

Abstract: An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.

公开(公告)号：US11502254B2

公开(公告)日：2022-11-15

申请号：US16147199

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Oleg Golonzka

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.

公开(公告)号：US11380838B2

公开(公告)日：2022-07-05

申请号：US16024522

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Justin Brockman ,  Conor Puls ,  Stephen Wu ,  Christopher Wiegand ,  Tofizur Rahman ,  Daniel Ouellette ,  Angeline Smith ,  Andrew Smith ,  Pedro Quintero ,  Juan Alzate-Vinasco ,  Oleg Golonzka

IPC: H01L43/02 ,  G11C11/16 ,  H01L21/768 ,  H01L23/528 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.

公开(公告)号：US10861851B2

公开(公告)日：2020-12-08

申请号：US15828259

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

IPC: H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L29/78

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

公开(公告)号：US20200343445A1

公开(公告)日：2020-10-29

申请号：US16396465

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Nathan Strutt ,  Albert Chen ,  Pedro Quintero ,  Oleg Golonzka

IPC: H01L45/00 ,  G11C13/00

Abstract: A memory apparatus includes an interconnect in a first dielectric above a substrate and a structure above the interconnect, where the structure includes a diffusion barrier material and covers the interconnect. The memory apparatus further includes a resistive random-access memory (RRAM) device coupled to the interconnect. The RRAM device includes a first electrode on a portion of the structure, a stoichiometric layer having a metal and oxygen on the first electrode, a non-stoichiometric layer including the metal and oxygen on the stoichiometric layer. A second electrode including a barrier material is on the non-stoichiometric layer. In some embodiments, the RRAM device further includes a third electrode on the second electrode. To prevent uncontrolled oxidation during a fabrication process a spacer may be directly adjacent to the RRAM device, where the spacer includes a second dielectric.

公开(公告)号：US10770651B2

公开(公告)日：2020-09-08

申请号：US16463326

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Kaan Oguz ,  Daniel G. Ouellette ,  Brian Maertz ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Brian S. Doyle ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12 ,  H01L43/00

Abstract: A material layer stack for a pSTTM device includes a fixed magnetic layer, a tunnel barrier disposed above the fixed magnetic layer and a free layer disposed on the tunnel barrier. The free layer further includes a stack of bilayers where an uppermost bilayer is capped by a magnetic layer including iron and where each of the bilayers in the free layer includes a non-magnetic layer such as Tungsten, Molybdenum disposed on the magnetic layer. In an embodiment, the non-magnetic layers have a combined thickness that is less than 15% of a combined thickness of the magnetic layers in the stack of bilayers. A stack of bilayers including non-magnetic layers in the free layer can reduce the saturation magnetization of the material layer stack for the pSTTM device and subsequently increase the perpendicular magnetic anisotropy.